“PCI-Express®: Continued Evolution of the Open Innovation Slot in Computing Platforms”

For over two decades, the Peripheral Component Interconnect Express® (PCIe®) architecture has served as the ubiquitous backbone for the global compute continuum. This talk explores the multi-generational innovations that have enabled PCIe to double its bandwidth through eight generations while maintaining its hallmark of strict backward compatibility and cost-effective, power-efficient performance. We will examine the architectural evolution of Unordered I/O and Multi-Link capabilities, which provide scalable performance and enhanced Reliability, Availability, and Serviceability (RAS) through multi-pathing—all while preserving foundational producer-consumer ordering semantics.
Furthermore, we will discuss the strategic expansion of the ecosystem through Compute Express Link (CXL), which overlays coherency and memory protocols on the PCIe physical layer to address the ‘memory wall’ and enable distributed computing. Finally, we look toward the next frontier: PCIe over optical, which extends reach to enable native PCIe and CXL-based resource pooling and sharing at the Rack and Pod scale.

Dr. Debendra Das Sharma is an Intel Senior Fellow and Chief I/O Architect, Platform Engineering Group, at Intel Corporation. He is a member of NAE, Fellow of IEEE, and Fellow of International Academy of AI Sciences (AAIS). He is a leading expert on I/O subsystem and interface architecture. He delivers Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), and Intel’s Coherency interconnect, as well as their implementation.

Dr. Das Sharma is a member of the Board of Directors and treasurer for the PCI Special Interest Group (PCI-SIG). He has been a lead contributor to PCIe specifications since its inception. He is the co-inventor of CXL, a founding member of the CXL consortium, and chairs the CXL consortium. He co-led the CXL Board Technical Task Force (2019-2024), and is a leading contributor to CXL specifications. He co-invented the chiplet interconnect standard UCIe and is the chair of the UCIe consortium.

Dr. Das Sharma has a bachelor’s in technology (with honors) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst. He holds 230+ US patents and 500+ patents world-wide. He is a frequent keynote/ plenary speaker, distinguished lecturer, invited speaker, invited columnist, and panelist at Nature Electronics, IEEE International Test Conference, IEEE Hot Interconnects, IEEE Cool Chips, IEEE 3DIC, SNIA SDC, PCI-SIG Developers Conference, CXL consortium, Open Server Summit, Open Fabrics Alliance, Flash Memory Summit, Intel Innovation, and Universities (CMU, Texas A&M, Georgia Tech, UIUC, UC Irvine). He has been awarded the Distinguished Alumnus Award from Indian Institute of Technology, Kharagpur in 2019, the IEEE Region 6 Outstanding Engineer Award in 2021, the first PCI-SIG Lifetime Contribution Award in 2022, the IEEE Circuits and Systems Industrial Pioneer Award in 2022, and the IEEE Computer Society Edward J. McCluskey Technical Achievement Award in 2024.