Miodrag Potkonjak

Professor

Computer Science Department
UCLA 

3532G Boelter Hall
Los Angeles, CA 90095-1596
tel: (310) 825-0790, fax: (310) 794-5056

 

e-mail: miodrag@cs.ucla.edu

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Publications | Bio

Book

Book Chapters

Journal Papers

Conference Papers

Patents

Books

  1. G. Qu, M. Potkonjak, Intellectual Property Protection in VLSI Design Theory and Practice, Kluwer Publishing, ISBN 1-4020-7320-8, February 2003.

Book Chapters

  1. J. Rabaey, C. Chu, P. Hoang, M. Potkonjak, "Synthesis of Datapath Architectures", in "Anatomy of a Silicon Compiler", ed. by R.W. Brodersen, Kluwer Academic Publishers, Boston, MA, pp. 221-249, 1992.

  2. M. Potkonjak, J. Rabaey, "Exploring the Algorithmic Design Space Using High Level Synthesis", in "VLSI Design Methodologies for Digital Signal Processing Architectures", ed. by M.A. Bayoumi, Kluwer, Boston, MA, pp. 131-167, 1994.

  3. I. Hong, D. Kirovski, M. Potkonjak, "High Level Synthesis", in  "Wiley Encyclopedia of Electrical and Electronic Engineering", John Wiley and Sons.

  4. S. Dey, A. Parker, M. Potkonjak, Y. Tirat-Gefen, "Critical Path Analysis", in "Wiley Encyclopedia of Electrical and Electronic Engineering", John Wiles and Sons.

  5. S. Megerian, M. Potkonjak,"Wireless Sensor Networks", in "Encyclopedia of Telecommunications", Wiley Publishers, 2002.

  6. J. L. Wong, J. Feng, D. Kirovski, M. Potkonjak, "Security and Privacy in Sensor Networks", in "Wireless Sensor Networks", Kluwer Academic Publishers, 2004.

  7. F. Koushanfar, M. Potkonjak, A. Sangiovanni-Vincentelli, "Fault Tolerance in Wireless Sensor Networks", in "Handbook of Sensor Networks: Compact Wireless and Wired Sensing Systems", CRC press, 2004.

  8. S. Slijepcevic, J. L. Wong, M. Potkonjak, "Security and Privacy Protection in Wireless Sensor Networks", in "Handbook of Sensor Networks: Compact Wireless and Wired Sensing Systems", CRC press, 2004.

  9. J. Feng, F. Koushanfar, M. Potkonjak, "Sensor Network Architecture",  in "Handbook of Sensor Networks: Compact Wireless and Wired Sensing Systems", CRC press, 2004.

  10. J. Feng, F. Koushanfar, M. Potkonjak, "Localized Algorithms for Sensor Networks",  in "Handbook of Sensor Networks: Compact Wireless and Wired Sensing Systems", CRC press, 2004.

Journal Papers

  1. Z. Obradovic, M. Potkonjak, M. Obradovic, "Design of Efficient Algorithms for VLSI Systolic Arrays", Informatics, Vol. 21, No. 2, pp. 153-159, 1987.

  2. J. Rabaey, C. Chu, P. Hoang, M. Potkonjak, "Fast Prototyping of Datapath-Intensive Architectures", IEEE Design and Test of Computers, Vol. 8, No. 2, pp. 40-51, June 1991.

  3. M. Potkonjak, J. Rabaey, "Scheduling Algorithms for Hierarchical Data Control Flow Graphs", International Journal of Circuits Theory and Applications, Vol. 20, No. 3, pp. 217-234, May-June 1992.

  4. M. Potkonjak, J. Rabaey, "Optimizing Resource Utilization Using Transformations", IEEE Transactions on CAD, Vol. 13, No. 3, pp. 277-292, March 1994.

  5. J. Rabaey, M. Potkonjak, "Estimating Implementation Bounds for Real Time Application Specific Circuits", IEEE Transaction on CAD, Vol. 13, No. 6, pp. 669-683, June 1994.

  6. M. Potkonjak, J. Rabaey, "Optimizing Throughput and Resource Utilization using Pipelining: Transformation Based Approach", Journal of VLSI Signal Processing, Vol. 8, No. 2, pp. 117-130, October 1994.

  7. A.P. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, R. Brodersen, "Optimizing Power Using Transformations", IEEE Transactions on CAD, Vol. 14, No. 1, pp. 12-31, January 1995.

  8. M. B. Srivastava, M. Potkonjak, "Optimum and Heuristic Transformation Techniques for Simultaneous Optimization of Latency and Throughput", IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol. 3, No. 1, pp. 2-19, March 1995.

  9. M. Potkonjak, S. Dey, R. K. Roy, "Considering Testability at Behavioral Level: Use of Transformations for Partial Scan Cost Minimization Under Timing and Area Constraints", IEEE Transactions on CAD, Vol. 14, No. 5, pp. 531-546, May 1995.

  10. M. Potkonjak, P. Ashar, S. Dey, T. Misawa, R. K. Roy, "Synthesis Techniques for Low Power Digital Designs", NEC Research and Development Journal, Vol. 36, No 1, pp. 83-102, January 1995.

  11. M. Potkonjak, S. Dey, R.K. Roy, "Behavioral Synthesis of Area-Efficient Testable Designs Using Interaction Between Hardware Sharing and Partial Scan", IEEE Transactions on CAD, Vol. 14, No. 9, pp. 1141-1154, September 1995.

  12. M. Potkonjak, M.B. Srivastava, A. Chandrakasan, "Multiple Constant Multiplications: Efficient and Versatile Framework and Algorithms for Exploring Common Subexpression Elimination", IEEE Transaction on CAD, Vol. 15, No. 2, pp. 151-165, February 1996.

  13. M. R. Corazao, M. Khalaf, L. Guerra, M. Potkonjak, J. Rabaey, "Performance Optimization using Template Mapping for Datapath-Intensive High-Level Synthesis", IEEE Transaction on CAD, Vol. 15, No. 8, pp. 877-888, August 1996.

  14. S. Dey, M. Potkonjak, "Non-Scan Design -for-Testability Techniques using RT-Level Design", IEEE Transaction on CAD, Vol. 16, No. 12, pp. 1488-1506, December 1997.

  15. L. M. Guerra, M. Potkonjak, J. Rabaey, "Behavioral-Level Synthesis of Heterogeneous BISR Reconfigurable ASICs", IEEE Transactions on VLSI Systems, Vol. 6, No. 1, pp. 158-167, January 1998.

  16. S. Dey, V. Gangaram, M. Potkonjak, "A Controller Redesign Techniques To Enhance Testability of Controller-Data Path Circuits", IEEE Transaction on CAD, Vol. 17, No. 2, pp. 157-168, February 1998.

  17. J. Lach, W. Mangione-Smith, Miodrag Potkonjak, "Low Overhead Fault-tolerant FPGA Systems", IEEE Transactions on VLSI Systems, Vol. 6, No. 2, pp. 212-221, June 1998.

  18. M. Potkonjak, M.B. Srivastava, "Behavioral Optimization Using the Manipulation of Timing Constraints", IEEE Transaction on CAD, Vol. 17, No. 10, pp. 936-947, October 1998.

  19. C. Lee, M. Potkonjak, W.H. Wolf, "Synthesis of Hard Real-Time Application Specific Systems", Design Automation for Embedded Systems, Journal, Vol. 4, No. 4, pp. 215-242, October 1998.

  20. I. Hong, D. Kirovski, K. Kornegay, M. Potkonjak, "High-level Synthesis Techniques for Functional Test Pattern Execution", Integration, the VLSI journal, Vol. 25, No. 2, pp. 161-180, November 1998.

  21. N. Shnidman, W. Mangione-Smith, M. Potkonjak, "On-line Fault Detection for Bus-based Field Programmable Gate Arrays", IEEE Transactions on VLSI Systems, Vol. 6, No. 4, pp. 656-666, December 1998.

  22. M. Potkonjak, J. Rabaey, "Algorithm Selection: A Quantitative Optimization Intensive Approach", IEEE Transaction on CAD, Vol. 18, No. 5, pp. 524-533, May 1999.

  23. S. Dao, E. Shek, A. Vellaikal, R. Muntz, L. Zhang, M. Potkonjak, O. Wolfson, "Semantic Multicast: Intelligently Sharing Collaborative Sessions",ACM Computing Surveys, Vol. 31, No. 2, pp. 27-33, June 1999.

  24. D. Kirovski, C. Lee, M. Potkonjak, W. Mangione-Smith, "Application-driven Synthesis of Memory-Intensive Systems-on-Chip", IEEE Transaction on CAD, Vol. 18, No. 9, pp. 1316-1326, September 1999.

  25. I. Hong. M. Potkonjak, M.C. Papaefthymiou, "Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors", Design Automation for Embedded Systems Journal, Vol. 4, No. 4, pp. 311-327, October 1999.

  26. I. Hong, M. Potkonjak, R. Karri, "Power Minimization using Divide-and-Conquer Techniques for Minimization of the Number of Operations", ACM Transaction on Design Automation, Vol. 4, No. 4, pp. 405-429, October 1999.

  27. M. Potkonjak, W.Wolf, "A Methodology and Algorithms for the Design of Hard Real-Time Multitasking ASIC", ACM Transaction on Design Automation, Vol. 4, No. 4, pp. 430-459, October 1999.

  28. M. Potkonjak, "Low Power and Quality of Service: From Algorithms and Architectures to RTOSs and Compilers", IEEE Concurrency, Vol. 7, No. 4, pp. 9-10, October 1999.

  29. D. Kirovski, M. Potkonjak, L.M. Guerra, "Improving the observability and controllability of datapaths for emulation-based debugging", IEEE Transaction on CAD, Vol. 18, No. 12, pp. 1529-1541, November 1999.

  30. I. Hong, D. Kirovski, G. Qu, M. Potkonjak, M.B. Srivastava, "Power Optimization of Variable Voltage Core-based Systems", IEEE Transaction on CAD, Vol.18, No.12, pp. 1702-1714, December 1999.

  31. M. Potkonjak, J. Rabaey, "Maximally and Arbitrarily Fast Hardware Efficient Implementation of Linear and Feedback Linear Computations", IEEE Transaction on CAD, Vol. 19, No. 1, pp. 30-43, January 2000.

  32. D. Kirovski, M. Potkonjak, L.M. Guerra, "Cut-based Debugging for Programmable Systems-on-Chip", IEEE Transactions on VLSI Systems, Vol. 8, No. 1, pp. 40-51, February 2000.

  33. M.C. Papaefthymiou, K.N. Lalgudi, M. Potkonjak, "Optimizing Computations for Effective Block-Processing", ACM Transaction on Design Automation, Vol.5, No.3, pp. 604-630, July 2000.

  34. J. Lach, W. Mangione-Smith, Miodrag Potkonjak, "Enhanced FPGA Reliability Through Efficient Runtime Fault Recovery", IEEE Transactions on Reliability, Vol. 49, No. 49, pp. 296-304, September 2000.

  35. R. Karri, K. Kim, M. Potkonjak, "Computer aided design of fault-tolerant application specific programmable processors". IEEE Transactions on Computers, Vol.49, No.11, pp. 1272-1284, November 2000.

  36. C. Lee, J. Kin, M. Potkonjak, W. Mangione-Smith, "Exploring Hypermedia Processor Design Space", Journal of VLSI Signal Processing, Vol. 27, No.1-2, pp.171-186, February 2001.

  37. F. Koushanfar, D. Kirovski, I. Hong, M. Potkonjak, M.C. Papaefthymiou, "Symbolic debugging of embedded hardware and software", IEEE Transactions on CAD, Vol. 20. No. 3, pp. 392-401, March 2001.

  38. J. Kin, C. Lee, W. Mangione-Smith, M. Potkonjak, "Exploring the Diversity of Multimedia Systems", IEEE Transactions on VLSI Systems, Vol. 9, No.3, pp. 474-485, June 2001.

  39. A. B. Kahng, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang, G. Wolfe, "Constraint-based watermarking techniques for design IP protection", IEEE Transactions on CAD, Vol. 20, No. 10, pp. 1236 -1252, October 2001.

  40. J. Lach, W. H. Mangione-Smith, M. Potkonjak, "Fingerprinting Techniques for Field Programmable Gate Array Intellectual Property Protection", IEEE Transactions on CAD, Vol. 20, No. 10, pp. 1253 -1261, October 2001.

  41. I Hong, M. Potkonjak, "Heterogeneous BISR using system level synthesis", IEEE Transactions on Reliability, 2001.

  42. G. Qu, M. Potkonjak, "System Synthesis of Synchronous Multimedia Applications", IEEE Transactions on Embedded Computing Systems, Special Issue on Memory Systems, Vol. 2, No. 1, pp. 74-97, Feburary 2002.

  43. S. Megerian, F. Koushanfar, G. Qu, G. Veltri, M. Potkonjak. "Exposure In Wireless Sensor Networks: Theory And Practical Solutions", Journal of Wireless Networks, Vol. 8, No. 5, ACM Kluwer Academic Publishers, pp. 443-454, September 2002.

  44. S. Slijepcevic, S. Megerian, M. Potkonjak. "Location Errors in Wireless Embedded Sensor Networks: Sources, Models, and Effects on Applications" ACM Mobile Computing and Communications Review, Vol. 6, No. 3, pp. 67-78, July 2002.

  45. J. L. Wong, Miodrag Potkonjak, "Watermarking Graph Partitioning Solutions", IEEE Transactions on CAD, Vol. 21, No. 10, October 2002.

  46. G. Qu, N. Kawabe, K. Usami, M. Potkonjak, "Code Coverage-based Power Estimation Techniques for Microprocessors", Journal of Circuits, Systems, and Computers, Vol. 11, No. 5, pp. 1-18, October 2002.

  47. G. Qu, M. Potkonjak, "Techniques for Energy-Efficient Communication Pipeline Design", IEEE Transactions on VLSI, October 2002. 

  48. D. Kirovski and M. Potkonjak, "Local Watermarks: Methodology and Application to Behavioral Synthesis", IEEE Transactions on CAD, Vol. 22, No. 9, pp. 1277-1284, September 2003.

  49.  J. L. Wong, G. Qu, and M. Potkonjak, "Optimization-Intensive Watermarking Techniques for Decision Problems", IEEE Transactions on CAD, Vol. 23, No. 1, pp. 119 - 127, January 2004.

  50.  J. L. Wong, M. Potkonjak, Sujit Dey, "Optimizing Designs Using the Addition of Deflection Operations", IEEE Transactions on CAD, Vol. 23, No. 1, pp. 50-59, January 2004. 

  51. I. Hong, M. Potkonjak, R. Karri, "A Heterogeneous Built-in Self-Repair Approach Using System-Level Synthesis Flexibility", IEEE Transactions on Reliability, Vol. 53 , No. 1 , pp. 93-101, March 2004.

  52. J. L. Wong, D. Kirovski,  M. Potkonjak, "Computational forensic techniques for intellectual property protection", IEEE Transactions on CAD, Vol. 23 , No.  6, pp. 987-994,  June 2004.

  53. J.L. Wong, F. Koushanfar,  S. Meguerdichian , M. Potkonjak,"Probabilistic constructive optimization techniques",  IEEE Transactions on CAD, Vol. 23 , No.  6, pp. 859 - 868, June 2004.

  54. J. L. Wong, G. Qu,  M. Potkonjak, "Power minimization in QoS sensitive systems", IEEE Transactions on TVLSI, Vol. 12 , No. 6 , pp. 553 - 561, June 2004.

  55. A. E. Caldwell, H.J. Choi, A. B. Kahng, S. Mantik, M. Potkonjak, G. Qu, and  J. L. Wong, "Effective Iterative Techniques for Fingerprinting Design IP", IEEE Transactions on CAD, Vol. 23 , No.  2 , pp. 208-215, Febuary 2004.

  56. J. L. Wong, R. Majumdar,  M. Potkonjak, "Fair watermarking using combinatorial isolation lemmas", IEEE Transactions on CAD, Vol. 23 , No. 11 , pp. 1566-1574, November 2004.

  57. S. Megerian, F. Koushanfar, M. Potkonjak,  M. B. Srivastava, "Worst and Best-Case Coverage in Sensor Networks", IEEE Transactions on  Mobile Computing,  Vol. 4 , No. 1, pp. 84-92, Jan-Feb 2005.

  58. D. Kirovski, M. Drinic, M. Potkonjak, "Engineering Change Protocols for Behavioral and System Synthesis",  IEEE Transactions on CAD, to appear, 2005.

Conference Papers

  1. N. Aleksic, M. Potkonjak, "Editor", B&H Informatics Symposium, pp. 160-167, Jahorina, Yugoslavia, February 1986.

  2. N. Aleksic, M.Potkonjak, "Formatted input-output in PL/M-86", ETAN Conference, Vol. III, pp. 99-104, Herceg-Novi, Yugoslavia, June 1986.

  3. M. Potkonjak, N. Aleksic, "NP-Complete Problems in Communications", ETAN Conference, Vol. IV, pp. 445-450, Herceg-Novi, Yugoslavia, June 1986.

  4. Z. Obradovic, M. Potkonjak, "A New Heuristic Algorithm for Traveling Salesman and Related Problems", 8th International Symposium Computer at the University, pp. D.12 1-4, Cavtat, Yugoslavia, May 1986.

  5. N. Aleksic, M. Potkonjak, "A Speech Model Generator", 8th International Symposium Computer at the University, pp. 6R.10 1-6, Cavtat, Yugoslavia, May 1986.

  6. M. Potkonjak, N. Aleksic, "Supervision of the Maximum Possible Number of Radio-Emissions," 3rd International Conference on Systems Research Informatics & Cybernetics", pp. 8.4. 1-6, Baden-Baden, Germany, August 1986.

  7. M. Potkonjak, "Application of a Fast String Searching Algorithm in Signal Processing," 3rd International Conference on Systems Research Informatics & Cybernetics", pp. 3.1. 1-6, Baden-Baden, Germany, August 1986.

  8. N. Aleksic, M. Potkonjak, "A PCM Spectrum Model with additive Gaussian Noise", 9th International Symposium Computer at the University, pp. 9R.09 1-6, Cavtat, Yugoslavia, May 1987.

  9. M. Potkonjak, "New Variation at ICAI: Resolving Application Limitations and Possibilities of Artificial Intelligence in Computer-Aided Instruction", 9th International Symposium Computer at the University, pp. 9R.09 1-6, Cavtat, Yugoslavia, May 1987.

  10. Z. Obradovic, M. Potkonjak, "Software Speed-up of VLSI Systolics with Idle Cells", 9th International Symposium Computer at the University, pp. 2S.01 1-4, Cavtat, Yugoslavia, May 1987.

  11. M. Potkonjak, "Programming Languages and Data Organization", 9th International Symposium Computer at the University, pp. 1S.03 1-4, Cavtat, Yugoslavia, May 1987.

  12. M. Potkonjak, J.Rabaey, "A Scheduling and Resource Allocation Algorithm for Hierarchical Signal Flow Graphs", 26th ACM/IEEE Design Automation Conference, Las Vegas, NV, pp. 7-12, June 1989.

  13. C. Chu, M. Potkonjak, M. Thaler, J. Rabaey, "HYPER: An Interactive Synthesis Environment for High Performance Real Time Applications", Proceedings on 1989 IEEE ICCD, Cambridge, MA, pp. 432-435, October 1989.

  14. J. Rabaey, M. Potkonjak, "Resource Driven Synthesis in the HYPER System", 1990 IEEE 1991 IEEE International Symposium on Circuits and Systems, New Orleans, LA, pp. 2592-2595, May 1990.

  15. M. Potkonjak, J.Rabaey, "Retiming for Scheduling", VLSI Signal Processing Workshop, San Diego, CA, Vol. IV, pp. 23-32, IEEE Press, November 1990.

  16. J. Rabaey, M. Potkonjak, "Complexity Estimations for Real Rime Application Specific Circuits", 17th European Solid-State Circuits Conference, Milan, Italy, pp. 201-204, September 1991.

  17. M. Potkonjak, J. Rabaey, "Optimizing Resource Utilization Using Transformations", IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pp. 88-91, November 1991.

  18. M. Potkonjak, J. Rabaey, "Fast Implementation of Recursive Programs Using Transformations", 1992 International Conference on Acoustic, Speech, and Signal Processing, San Francisco, CA, pp. 569-572, March 1992.

  19. M. Potkonjak, J. Rabaey, "Probabilistic Rejectionless Anti-Voter Optimization Algorithm", 1992 IEEE International Symposium on Circuits and Systems, San Diego, CA, pp. 1451-1454, May 1992.

  20. M. Potkonjak, J. Rabaey, "Pipelining: Just Another Transformation", Proceedings 1992 Application Specific Array Processors, Oakland, CA, pp. 163-175, August 1992.

  21. D.C. Chen, L.M. Guerra, E.H. Ng, M. Potkonjak, D.P. Schultz, J. Rabaey, "An Integrated System for rapid Prototyping of High Performance Algorithm Specific Data Paths", Proceedings 1992 Application Specific Array Processors, Oakland, CA, pp. 134-148, August 1992.

  22. A.P. Chandrakasan, M. Potkonjak, J. Rabaey, R. Brodersen, "An Approach for Power Minimization Using Transformations", 1992 IEEE Workshop on VLSI Signal Processing, Napa Valley, CA, pp. 500-503, October 1992.

  23. M. Potkonjak, J. Rabaey, "Maximally Fast and Arbitrarily Fast Implementation of Linear Computations", ICCAD-92 IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pp. 304-308, November 1992.

  24. S. Dey, M. Potkonjak, S. Rothweiler, "Performance Optimization of Sequential Circuits by Eliminating Retiming Bottlenecks", ICCAD-92 IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pp. 504-509, November 1992.

  25. A.P. Chandrakasan, M. Potkonjak, J. Rabaey, R. Brodersen, "Hyper-LP: A Design System for Power Minimization using Architectural Transformations", ICCAD-92 IEEE International Conference on Computer-Aided Design, Santa Clara, CA, pp. 300-303, November 1992. Distinguished Paper Citation.

  26. M. Potkonjak, J. Rabaey, "On Unlimited Parallelism of DSP Arithmetic Computations", 1993 International Conference on Acoustic, Speech, and Signal Processing, Minneapolis, MN, pp. 381-384, April 1993.

  27. S. Chakradhar, S. Dey, M. Potkonjak, S. Rothweiler, "Sequential Circuits Delay Optimization Using Global Path Delays", 30th ACM/IEEE DAC Design Automation Conference, Dallas, TX, pp. 483-489, June 1993. Best Paper Award Candidate.

  28. Z. Iqbal, M. Potkonjak, S. Dey, A. Parker, "Critical Path Minimization Using Retiming and Algebraic Speed-Up", 30th ACM/IEEE DAC Design Automation Conference, Dallas, TX, pp. 573-577, June 1993.

  29. L. Guerra, M. Potkonjak, J. Rabaey, "High Level Synthesis for Efficient Built-In Self Repair", 1993 International Workshop on Defect and Fault Tolerance in VLSI Systems, Venice, Italy, pp. 41-48, October 1993.

  30. M. Potkonjak, L. Guerra, J. Rabaey, "Heterogeneous BISR Technique for Yield and Reliability Enhancement using High Level Synthesis Transformations", Proceedings of the International Conference on Application Specific Array Processors, Venice, Italy, pp. 454-465, October 1993.

  31. M. Potkonjak, J. Rabaey, "Exploring The Algorithmic Design Space Using High Level Synthesis", VLSI Signal Processing Workshop, Eindhoven, Netherlands, pp.123-131,  October 1993.

  32. M. Potkonjak, S. Dey, Z. Iqbal, A. Parker, "High Performance Embedded System Optimization Using Algebraic and Generalized Retiming Techniques", IEEE International Conference on Computer Design, Boston, MA, pp. 498-504, October 1993.

  33. M.R. Corazao, M. Khalaf, L. Guerra, M. Potkonjak, J. Rabaey, "Instruction Set Mapping for Performance Optimization", ICCAD93 International Conference on Computer-Aided Design, Santa Clara, CA, pp. 518-521, November 1993.

  34. L. Guerra, M. Potkonjak, J. Rabaey, "High Level Synthesis for Reconfigurable Datapath Structures", ICCAD93 International Conference on Computer-Aided Design, Santa Clara, pp. 26-29, November 1993. Distinguished Paper Citation.

  35. S. Dey, M. Potkonjak, R. Roy, "Exploiting Hardware-Sharing in High Level Synthesis for partial Scan Optimization", ICCAD93 International Conference on Computer-Aided Design, Santa Clara, pp. 20-25, November 1993. Distinguished Paper Citation.

  36. M. B. Srivastava, M. Potkonjak, "Transforming Linear Systems for Joint Latency and Throughput Optimization", EDAC-94 European Design Automation Conference, Paris, France, pp. 267-271, 1994.

  37. L.M. Guerra, M. Potkonjak, J. Rabaey, "Concurrency Characteristics in DSP Programs", ICASSP-94 International Conference on Acoustic, Speech, and Signal Processing, Minneapolis, MN, Vol. 2, pp. 433-436, April 1994.

  38. S.Dey, M. Potkonjak, R.K. Roy, "Behavioral Synthesis of Low-Cost Partial Scan Designs for DSP Applications", ICASSP-94 International Conference on Acoustic, Speech, and Signal Processing, Minneapolis, MN, Vol. 2, pp. 441-444, April 1994.

  39. M. Potkonjak, M. Srivastava, "Design of High Throughput, Low Latency and Low Cost Structures for Linear Systems", ICASSP-94 International Conference on Acoustic, Speech, and Signal Processing, Minneapolis, MN, Vol. 2, pp. 497-500, April 1994.

  40. S. Dey, M. Potkonjak, R. K. Roy, "Synthesizing Designs with Low-Cardinality Minimum Feedback Vertex Set for Partial Scan Application", VLSI Test Symposium, Cherry Hill, pp. 2-7, April 1994.

  41. M. Potkonjak, M.B. Srivastava, A. Chandrakasan, "Efficient Substitution of Multiple Constant Multiplications by Shifts and Additions using Iterative Pairwise Matching", DAC-94 31th ACM/IEEE DAC Design Automation Conference, San Diego, CA, pp. 189-194, June 1994.

  42. M. Potkonjak, S. Dey, "Optimizing Resource Utilization and Testability using Hot Potato Techniques", DAC-94 31th ACM/IEEE DAC Design Automation Conference, San Diego, CA, pp. 201-205, June 1994.

  43. M. Potkonjak, M. B. Srivastava, "Behavioral Synthesis of High Performance, Low Cost, and Low Power Application Specific Processors for Linear Computations", Proceedings of the International Conference on Application Specific Array Processors, pp. 45-56, San Francisco, CA, August 1994.

  44. S. Dey, M. Potkonjak, "Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs", International Test Conference, Washington, DC, pp. 184-193, October 1994.

  45. R.K. Roy, S. Dey, M. Potkonjak, "Test Synthesis Using High-Level Design Informations", International Test Symposium at International Test Conference, Washington, DC, pp. 311 - 316, 1994.

  46. S. Dey, M. Potkonjak, "Techniques for At-Speed Testing of VLSI ASIC Designs", VLSI Signal Processing Workshop, San Diego, CA, pp. 236-245, October 1994.

  47. L. Guerra, M. Potkonjak, J. Rabaey, "System-Level Design Guidance Using Algorithm Properties", VLSI Signal Processing Workshop, San Diego, pp. 73-82, October 1994.

  48. M. Potkonjak, J. Rabaey, "Area-time VLSI High Level Synthesis Laws: Theory and Practice", VLSI Signal Processing Workshop, San Diego, pp. 53-62, October 1994.

  49. S. Dey, M. Potkonjak, "Non-Scan Design-for-Testability of RT-Level Data Paths", ICCAD94 International Conference on Computer-Aided Design, Santa Clara, CA, pp. 640-645, November 1994.

  50. M. Potkonjak, J. Rabaey, "Algorithm Selection: A Quantitative Computation-Intensive Optimization Approach", ICCAD94 International Conference on Computer-Aided Design, Santa Clara, pp. 90-95, November 1994.

  51. J.M. Rabaey, M. Potkonjak, K. Wakabayashi, "Efficient Throughput Optimization of Feedback Linear Computations using Horner Scheme", ICASSP95 International Conference on Acoustic, Speech, and Signal Processing, Detroit, MI, Vol. 4, pp. 2659-2662, 1995.

  52. M. Potkonjak, J.M. Rabaey, "Power Minimization in DSP Application Specific Systems using Algorithm Selection", ICASSP95 International Conference on Acoustic, Speech, and Signal Processing, Detroit, MI, Vol. 4, pp. 2639-2642, 1995.

  53. J.C. DeSouza-Batista, M.Potkonjak, A. Parker, "Optimal ILP-based Approach for Throughput Optimization using Algorithm/Architecture Matching and Retiming", DAC-95 32nd ACM/IEEE DAC Design Automation Conference, San Francisco, CA, pp. 113-118, 1995.

  54. M. Potkonjak, M.B. Srivastava, "Rephasing: A Transformation Technique for the Manipulation of Timing Constraints", DAC-95 32nd ACM/IEEE DAC Design Automation Conference, San Francisco, CA, pp. 107-112, 1995. Best Paper Award Candidate.

  55. M. Potkonjak, S. Dey, R.K. Roy, "Synthesis-for-Testability Using Transformations", ASP-DAC95 Asia-South Pacific Design Automation Conference, Chiba, Japan, pp. 485-490, September 1995, Best Paper Award Candidate.

  56. M. B. Srivastava, M. Potkonjak, "Energy Efficient Implementation of Linear System on Programmable Processors", 1995 IEEE Workshop on VLSI Signal Processing VIII, Osaka, Japan, pp. 147-156, October 1995.

  57. M. Potkonjak, S. Dey, K.T. Kornegay, "Techniques for Implementation of At-Speed Testable, High Performance and Low Cost Linear Design", 1995 IEEE Workshop on VLSI Signal Processing VIII, Osaka, Japan, pp. 227-236, October 1995.

  58. M. Potkonjak, A. Chandrakasan, "Synthesis and Selection of DCT Algorithms using Behavioral Synthesis-Based Algorithm Space Exploration", IEEE ICIP-95 International Conference on Image Processing, Washington, DC, pp. 65-68, October 1995.

  59. M. Potkonjak, "Discrete-Relaxation-Based Heuristic Techniques for Video Algorithm/Architecture Matching and System Level Transformations", IEEE ICIP-95 Conference on Image Processing, Washington, DC, pp. 77-80, October 1995.

  60. M. Potkonjak, S. Dey, K. Wakabayashi, "Design-for-Debugging of Application Specific Designs", ICCAD95 International Conference on Computer-Aided Design, San Jose, CA, pp. 295-301, November 1995.

  61. M. Potkonjak, W. Wolf, "Cost Optimization in ASIC Implementation of Periodic Hard-Real Time Systems using Behavioral Synthesis Techniques", ICCAD95 International Conference on Computer-Aided Design, San Jose, CA, pp. 446-451, November 1995.

  62. S. Dey, V. Gangaram, M. Potkonjak, "A Controller-Based Design-for-Testability Techniques for Controller-Data Path Circuits", ICCAD95 International Conference on Computer-Aided Design, San Jose, CA, pp. 534-540, November 1995.

  63. M. B. Srivastava, M. Potkonjak, "Knowledge-Based Transformation Ordering: Implementing a Low Power and High Throughput Linear Computations", ICASSP96 International Conference on Acoustic, Speech, and Signal Processing, Atlanta, GE, Vol. 6, pp. 3335-3338, May 1996.

  64. M. Potkonjak, W. Wolf, "Heuristic Techniques for Synthesis of Hard Real-Time DSP Application Specific Systems", ICASSP96 International Conference on Acoustic, Speech, and Signal Processing, Atlanta, GE, Vol. II, pp. 1240-1243, May 1996.

  65. M. B. Srivastava, M. Potkonjak, "Power Optimization in Programmable Processors and ASIC Implementation of Linear Systems: Transformation-based Approach", DAC-96 33rd ACM/IEEE DAC Design Automation Conference, Las Vegas, NV, pp. 343-348, June 1996.

  66. K.N. Lalgudi, M.C. Papaefthymiou, M. Potkonjak, "Optimizing Systems for Effective Block-Processing: The k-Delay Problem", DAC-96 33rd ACM/IEEE DAC Design Automation Conference, Las Vegas, NV, pp. 714-719, June 1996.

  67. L. Guerra, M. Potkonjak, J. Rabaey, "Divide-and-Conquer Techniques for Global Throughput Optimization", VLSI Signal Processing Workshop, pp. 137-146, San Francisco, October 1996.

  68. K. Kim. R. Karri, M. Potkonjak, "Maximizing the fault-tolerance of application specific programmable signal processors", VLSI Signal Processing Workshop, pp. 137-146, San Francisco, October 1996.

  69. C. Lee, M. Potkonjak, W. Wolf, "System-level Synthesis of Application Specific Systems using A* Search and Generalized Force-Directed Heuristics", International Symposium on System Synthesis, pp. 2-7, San Diego, CA, November 1996.

  70. S. Dozy, I. Hong, M. Potkonjak, "Throughput Optimization in Disk-Based Real-time Application Specific Systems", International Symposium on System Synthesis, pp, 133-138, San Diego, November 1996.

  71. K. Kim. R. Karri, M. Potkonjak, "Heterogeneous Built-In-Resiliency of Application Specific Programmable Processors", ICCAD96 International Conference on Computer-Aided Design, pp. 406-411, San Jose, CA, November 1996.

  72. I. Hong, M. Potkonjak, "Power Optimization in Disk-Based Real-Time Application Specific Systems", ICCAD96 International Conference on Computer-Aided Design, pp. 634-637, San Jose, CA, November 1996.

  73. K. Kim. R. Karri, M. Potkonjak, "Configurable Spare Processors: A New Approach to System-Level Fault Tolerance", IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 295-303, Boston, MA, November 1996.

  74. I. Hong, M. Potkonjak, "Minimizing the Number of Operations in DSP Computations", ICASSP97 International Conference on Acoustic, Speech, and Signal Processing, pp. 659-662, April 1997.

  75. C. Lee, D. Kirovski, I. Hong, M. Potkonjak, "DSP Quant: Design, Validation, and Applications of DSP Hard Real-Time Benchmark", ICASSP97 International Conference on Acoustic, Speech, and Signal Processing, pp. 679-682, April 1997.

  76. M. Potkonjak, K. Kim, R. Karri, "Methodology for Behavioral Synthesis-Based Algorithm-Level Design Space Exploration: DCT Case Study", DAC-97 34th ACM/IEEE DAC Design Automation Conference, Anaheim, CA, pp. 252-257, June 1997.

  77. I. Hong, D. Kirovski, M. Potkonjak, "Potential-Driven Statistical Ordering of Transformations", DAC-97 34th ACM/IEEE DAC Design Automation Conference, Anaheim, CA, pp. 347-352, June 1997.

  78. K. Kim, R. Karri, M. Potkonjak, "Synthesis of Application Specific Programmable Processors", DAC-97 34th ACM/IEEE DAC Design Automation Conference, Anaheim, CA, pp. 353-358, June 1997.

  79. D. Kirovski, M. Potkonjak, "System-Level Synthesis of Low-Power Hard Real-Time Systems", DAC-97 34th ACM/IEEE DAC Design Automation Conference, Anaheim, CA, pp. 697-702, June 1997.

  80. Y. Li, M. Potkonjak, W. Wolf, "Advances in Real-Time Operating Systems", IEEE International Conference on Computer Design, pp. 388-392, Austin, TX, October 1997.

  81. N. Shnidman, W. Mangione-Smith, M. Potkonjak, "Fault Scanner for Reconfigurable Logic", Advanced Research VLSI Conference, pp. 238-255, September 1997.

  82. K. Kim, R. Karri, M. Potkonjak, "Micro-preemption Synthesis: An Enabling Mechanism for Multi-Task VLSI Systems", ICCAD97 International Conference on Computer-Aided Design, pp. 33-38, San Jose, CA, November 1997.

  83. D. Kirovski, C. Lee. M. Potkonjak, W. Mangione-Smith, "Application-driven Synthesis of Core-based Systems", ICCAD97 International Conference on Computer-Aided Design, pp. 104-107, San Jose, CA, November 1997.

  84. I. Hong, M. Potkonjak, R. Karri, "Power Optimization using Divide-and-Conquer Techniques for Minimization of the Number of Operations", ICCAD97 International Conference on Computer-Aided Design, pp. 108-111, San Jose, CA, November 1997.

  85. D. Kirovski, M. Potkonjak, "A Quantitative Approach to Functional Debugging", ICCAD97 International Conference on Computer-Aided Design, pp. 170-175, San Jose, CA, November 1997.

  86. C. Lee, W. Mangione-Smith, M. Potkonjak, "MediaBench: A Tool for Evaluating Multimedia and Communication Systems", MICRO-30 Conference, pp. 330-335, November 1997.

  87. I. Hong, M. Potkonjak, "Techniques for Functional Test Pattern Execution", ASP-DAC98 Asia-South Pacific Design Automation Conference, Yokohama, Japan, pp. 283-288, February 1998.

  88. I. Hong, M. Potkonjak, R. Karri, "Heterogeneous BISR-Approach Using System-Level Synthesis Flexibility", ASP-DAC98 Asia-South Pacific Design Automation Conference, Yokohama, Japan, pp. 289-294, February 1998.

  89. D. Kirovski, C. Lee, M. Potkonjak, W. Mangione-Smith, "Synthesis of Power-Efficient Systems-on-Silicon", ASP-DAC98 Asia-South Pacific Design Automation Conference, Yokohama, Japan, pp. 557-562, February 1998.

  90. C. Lee, M. Potkonjak, "Quantitative Selection of Media Benchmark", ASP-DAC98 Asia-South Pacific Design Automation Conference, Yokohama, Japan, pp. 105-110, February 1998.

  91. J. Lach, W. Mangione-Smith, M. Potkonjak, "Efficiently Supporting Fault Tolerance in FPGAs", ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 105-115, February 1998.

  92. J. Lach, W. Mangione-Smith, M. Potkonjak, "Fingerprinting Digital Circuits on Programmable Hardware", Information Hiding Workshop, pp. 16-31, Portland, Oregon, April 1998.

  93. J. Lach, W. Mangione-Smith, M. Potkonjak, "FPGA Fingerprinting Techniques for Protecting Intellectual Property", 1998 Custom Integrated Circuits Conference, Santa Clara, CA, pp. 299-302, May 1998.

  94. M. D. Ercegovac, D. Kirovski, G. Mustafa, M. Potkonjak, "Behavioral Synthesis Optimization using Multiple Precision Arithmetic", ICASSP98 International Conference on Acoustic, Speech, and Signal Processing, Seattle, WA, pp. 3113-3116, May 1998.

  95. I. Hong, M. Potkonjak, "Technique for Intellectual Property Protection of DSP designs", ICASSP98 International Conference on Acoustic, Speech, and Signal Processing, pp. 3133-3136, Seattle. WA, May 1998

  96. I. Hong, D. Kirovski, G. Qu, M. Potkonjak, M.B. Srivastava, "Power Optimization of Variable Voltage Core-based Systems", DAC-98 35th ACM/IEEE DAC Design Automation Conference, pp. 176-181, San Francisco, CA, June 1998.

  97. L. Guerra, M. Potkonjak, J. Rabaey, "A Methodology for Guided Behavioral-level Optimization", DAC-98 35th ACM/IEEE DAC Design Automation Conference, pp. 309-314, San Francisco, CA, June 1998.

  98. C. Lee, J. Kin, M. Potkonjak, W. Mangione-Smith, "Media Architecture: General Purpose vs. Application Specific Programmable Processor", DAC-98 35th ACM/IEEE DAC Design Automation Conference, pp. 321-326, San Francisco, CA, June 1998.

  99.   D. Kirovski, M. Potkonjak, "Efficient Coloring of a Large Spectrum of Graphs", DAC-98 35th ACM/IEEE DAC Design Automation Conference, pp. 427-432, San Francisco, CA, June 1998.

  100. A. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I.L. Markov, M. Potkonjak, P. Tucker, H. Wang, G. Wolfe, "Watermarking Techniques for Intellectual Property Protection", DAC-98 35th ACM/IEEE DAC Design Automation Conference, pp. 776-781, San Francisco, CA, June 1998.

  101. A. B. Kahng, S. Mantik, I.L. Markov, M. Potkonjak, P. Tucker, H. Wang, G. Wolfe, "Robust IP Watermarking Methodologies for Physical Design", DAC-98 35th ACM/IEEE DAC Design Automation Conference, pp. 782-787, San Francisco, CA, June 1998.

  102. H. Kim, W. Mangione-Smith, M. Potkonjak, "Protection Intellectual Ownership Rights of a Lossless Image Coder Through Hierarchical Watermarking", 1998 Signal Processing Systems Workshop, pp. 73-82, Boston, MA, October 1998.

  103. J. Lach, W. Mangione-Smith, M. Potkonjak, "Signature Hiding Techniques for FPGA Intellectual Property Protection", ICCAD98 International Conference on Computer-Aided Design, pp. 186-189, San Jose, CA, November 1998.

  104. G. Qu, M. Potkonjak, "Analysis of Watermarking Techniques for Graph Coloring Problem", ICCAD98 International Conference on Computer-Aided Design, pp. 190-193, San Jose, CA, November 1998.

  105. D. Kirovski, Y-Y. Hwang, M. Potkonjak, J. Cong, "Intellectual Property Protection by Watermarking Combinational Logic Synthesis Solutions", ICCAD98 International Conference on Computer-Aided Design, pp. 194-198, San Jose, CA, November 1998.

  106. C. Lee, M. Potkonjak, "A Quantitative Approach to development and Validation of Synthetic Benchmarks for Behavioral Synthesis", ICCAD98 International Conference on Computer-Aided Design, pp. 347-350, San Jose, CA, November 1998

  107. D. Kirovski, M. Potkonjak, L. Guerra, "Functional Debugging of Systems on Silicon", ICCAD98 International Conference on Computer-Aided Design, pp. 525-528, San Jose, CA, November 1998

  108. G. Qu, M. Potkonjak, "Techniques for Energy Minimization of Communication Pipelines", ICCAD98 International Conference on Computer-Aided Design, pp. 597-600, San Jose, CA, November 1998.

  109. I. Hong, M. B. Srivastava, M. Potkonjak, "On-Line Scheduling of Hard Real-Time Tasks on Variable Voltage Processor", ICCAD98 International Conference on Computer-Aided Design, pp. 653-656, San Jose, CA, November 1998.

  110. I. Hong, G. Qu, M. Potkonjak, M.B. Srivastava, "Synthesis Techniques for Low-Power Hard Real-Time Systems on Variable Voltage Processor", 1998 Real-Time System Symposium, pp. 178-187, Madrid, Spain, December 1998.

  111. J. Kin, C. Lee, W. Mangione-Smith, M. Potkonjak, "Hypermedia Processors: Design Space Exploration", 1998 Workshop on Multimedia Signal Processing, pp. 323-328, Los Angeles, CA, December 1998.

  112. J. Lach, W. Mangione-Smith, M. Potkonjak, "Efficient Support of Hardware Debugging Through FPGA Physical Design Partitioning", ACM International Symposium on Field Programmable Gate Arrays, p. 247, Monterey, February 1999.

  113. M. Potkonjak, D. Kirovski, "Engineering Change Protocols for Behavioral Synthesis", ICASSP99 International Conference on Acoustic, Speech, and Signal Processing, Vol. IV, pp. 1993-1996, Phoenix, AZ, March 1999.

  114. D. Kirovski, M. Potkonjak, "Synthesis of DSP Soft Real-Time Multiprocessor Systems-on-Silicon", ICASSP99 International Conference on Acoustic, Speech, and Signal Processing, Vol. IV, pp. 1901-1904, Phoenix, AZ, March 1999.

  115. K.T. Kornegay, G. Qu, M. Potkonjak, "Quality of Service and System Design", IEEE Workshop on VLSI `99, pp. 112-117, Orlando, FL, April 1999.

  116. A. Rashid, J. Asher, W. Mangione-Smith, M. Potkonjak, "Hierarchical Watermarking for Protection of DSP Filter Cores", 1999 Custom Integrated Circuits Conference, San Diego, CA, May 1999.

  117. G. Qu. D. Kirovski, M. Potkonjak, "Energy Minimization of Systems Pipelines Using Multiple Voltages", International Symposium on Circuits and Systems, Orlando, FL, Vol. 1, pp.362-365, June 1999.

  118. G. Qu, J. L. Wong, M. Potkonjak, "Optimization-Intensive Watermarking Techniques for Decision Problems", DAC-99 36th ACM/IEEE DAC Design Automation Conference, pp.33-36, New Orleans, LA, June 1999.

  119. J. Kin, C. Lee, W. Mangione-Smith, M. Potkonjak, "Power Efficient Media Processors: Design Space Exploration", DAC-99 36th ACM/IEEE DAC Design Automation Conference, pp. 321-326, New Orleans, LA, June 1999.

  120. M. Ercegovac, D. Kirovski, M. Potkonjak, "Low Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic" DAC-99 36th ACM/IEEE DAC Design Automation Conference, pp. 568-573, New Orleans, LA, June 1999.

  121. D. Kirovski, M. Potkonjak, "Engineering Change: Methodology and Applications to Behavioral and System Synthesis", DAC-99 36th ACM/IEEE DAC Design Automation Conference, pp. 604-609, New Orleans, LA, June 1999.

  122. J. Lach, W. Mangione-Smith, M. Potkonjak, "Robust FPGA Intellectual Property Protection through Multiple Small Watermarks", DAC-99 36th ACM/IEEE DAC Design Automation Conference, pp. 831-836, New Orleans, LA, June 1999.

  123. A. Caldwell, H-J, Choi, A.B. Kahng, S. Mantik, M. Potkonjak, G. Qu, J.L. Wong, "Effective Iterative Techniques for Fingerprinting Design IP", DAC-99 36th ACM/IEEE DAC Design Automation Conference, pp. 843-848, New Orleans, LA, June 1999

  124. I. Hong, M. Potkonjak, "Behavioral Synthesis Techniques for Intellectual Property Protection", DAC-99 36th ACM/IEEE DAC Design Automation Conference, pp.849-854, New Orleans, LA, June 1999.

  125. C. Lee, J. Kin, W. Mangione-Smith, M. Potkonjak, "Designing Power Efficient Hypermedia Processors", International Symposium on Low Power Electronics and Design, pp. 276-278, San Diego, CA, August 1999.

  126. J. Lach, W. Mangione-Smith, M. Potkonjak, "Algorithms for Efficient run-time fault recovery on diverse FPGA architectures", 1999 International Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 386-394, Albuquerque, NM, October 1999.

  127. J. Lach, W. Mangione-Smith, M. Potkonjak, "Enhanced Intellectual Property Protection for Digital Circuits on Programmable Hardware", Information Hiding Workshop, pp. 331-345, Dresden, Germany, September 1999

  128. G. Qu, M. Potkonjak, "Hiding Signatures in Graph Coloring Solutions", Information Hiding Workshop, pp. 391-408, Dresden, Germany, September 1999.

  129. G. Qu, M. Potkonjak, "Power Minimization using System-level Partitioning of Applications with QoS"., ICCAD99 International Conference on Computer-Aided Design, pp. 343-346, San Jose, CA, November 1999

  130. I. Hong, M. Potkonjak, L.M. Guerra, "Throughput Optimization of general non-linear computations", ICCAD99 International Conference on Computer-Aided Design, pp. 406-409. San Jose, CA, November 1999.

  131. D. Kirovski, M. Potkonjak, "Localized Watermarking: Methodology and Applications to Operation Scheduling", ICCAD99 International Conference on Computer-Aided Design, pp. 596-599, San Jose, CA, November 1999.

  132. A. Kahng, D. Kirovski, S. Mantik. M. Potkonjak, J.L. Wong, "Copy Detection for Intellectual Property Protection of VLSI Designs", ICCAD99 International Conference on Computer-Aided Design, pp. 600-604, San Jose, CA, November 1999.

  133. G. Qu, M. Mesarina, M. Potkonjak, "System Synthesis of Synchronous Multimedia Applications", International Symposium on System Synthesis, pp. 128-133, San Jose, CA, November 1999.

  134. J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Runtime Logic and Interconnect Fault Recovery on Diverse FPGA Architectures", Military and Aerospace Applications of Programmable Devices and Technologies International Conference, 1999.

  135. G. Qu, J.L. Wong, M. Potkonjak, "Fair Watermarking Techniques", Asia-South Pacific Design Automation Conference, pp. 55-60, Yokohama, Japan, January 2000.

  136. J. Kin, C. Lee, W. Mangione-Smith, M. Potkonjak, "A Technique for QoS System partitioning", Asia-South Pacific Design Automation Conference, pp. 241-246, Yokohama, Japan, January 2000.

  137. I. Hong, D. Kirovski, M. Potkonjak, M.C. Papaefthymiou, "Symbolic Debugging of Behavioral Specifications", ASP-DAC2000 Asia-South Pacific Design Automation Conference, pp. 397-400, Yokohama, Japan, January 2000.

  138. D. Kirovski, M. Potkonjak, "Localized watermarking: methodology and application to template mapping", 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing, Vol. 6, pp. 3235-3238, Istanbul, Turkey, 2000.

  139. G. Qu, M. Potkonjak , "Energy Minimization with Guaranteed Quality of Service", International Symposium on Low Power Electronics and Design, pp. 43-48, Rapallo, Italy, July 2000.

  140. G. Qu, M. Potkonjak , "Achieving Utility Arbitrarily Close to Optimal with Limited Energy", Energy Minimization with Guaranteed Quality of Service", International Symposium on Low Power Electronics and Design, pp. 125-130, Rapallo, Italy, July 2000.

  141. S. Meguerdichian, M. Potkonjak, "Watermarking while preserving the critical path", IEEE/ACM Design Automation Conference, pp. 108-111, Los Angeles, CA, June 2000.

  142. J. Lach, W.H. Mangione-Smith, M. Potkonjak, "Efficient error detection, localization and correction for FPGA-based debugging", IEEE/ACM Design Automation Conference, pp. 207-212, Los Angeles, CA, June 2000.

  143. D. Kirovski, D. Liu, J.L. Wong, M. Potkonjak, "Forensic engineering techniques for VLSI CAD tools", IEEE/ACM Design Automation Conference, pp. 580-586, Los Angeles, CA, June 2000.

  144. G. Qu, M. Potkonjak, "Fingerprinting intellectual property using constraint-addition", IEEE/ACM Design Automation Conference, pp. 587-592, Los Angeles, CA, June 2000.

  145. G. Qu, N. Kawabe, K. Usami, M. Potkonjak, "Function-level power estimation methodology for microprocessors", IEEE/ACM Design Automation Conference, pp. 810-813, Los Angeles, CA, June 2000.

  146. F. Koushanfar, V. Prabhu, M. Potkonjak, J.M. Rabaey, "Processors for mobile applications", International Conference on Computer Design, pp. 603-608, Austin, TX, September 2000.

  147. J. M. Burger, C. J. Cookson, D. Kirovski, D. P. Maher, M. Potkonjak, J. Welt, "Multimedia copyright enforcement on the Internet", ACM International Multimedia Conference, pp. 347-349, Los Angeles, CA, October 2000.

  148. F. Koushanfar, D. Kirovski, M. Potkonjak, "Symbolic debugging scheme for optimized hardware and software", IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000, pp. 40-43, San Jose, CA, November 2000.

  149. J.M. Rabaey, M. Potkonjak, F. Koushanfar, S. Li; T. Truong, "Challenges and opportunities in broadband and wireless communication designs", IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000, pp. 76-82, San Jose, CA, November 2000.

  150. M. Drinic, D. Kirovski, S. Meguerdichian, M. Potkonjak, "Latency-guided on-chip bus network design". IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000, pp. 420-423, San Jose, CA, November 2000.

  151. J. L. Wong, D. Kirovski, M. Potkonjak, "Computational Forensic Techniques for Intellectual Property Protection" Information Hiding Workshop, Pittsburgh, PA, April 2001.

  152. F. Koushanfar, G. Qu, M. Potkonjak, "Intellectual Property Metering", Information Hiding Workshop, Pittsburgh, PA, April 2001.

  153. S. Meguerdichian, F. Koushanfar, M. Potkonjak, M.B. Srivastava, "Coverage Problems in Wireless Ad-Hoc Sensor Networks," IEEE Infocom 2001,Vol 3, pp. 1380-1387, April 2001.

  154. D. Kirovski, M. Drinic, M. Potkonjak, "Hypermedia-Aided Design", IEEE/ACM Design Automation Conference, pp. 407-412, Las Vegas, NV, June 2001.

  155. G. Wolfe, J. L. Wong, M. Potkonjak, "Watermarking Graph Partitioning Solutions", IEEE/ACM Design Automation Conference, pp. 486-499, Las Vegas, NV, June 2001.

  156. S. Meguerdichian, F. Koushanfar, A. Mogre, D. Petranovic, M. Potkonjak, "MetaCores: Design and Optimization Techniques" IEEE/ACM Design Automation Conference, pp. 585-590, Las Vegas, NV, June 2001.

  157. S. Slijepcevic, M. Potkonjak, "Power efficient organization of wireless sensor networks", IEEE International Conference on Communications, vol. 2, pp 472-476, Helsinki, Finland, June 2001.

  158. S. Meguerdichian, F. Koushanfar, G. Qu, M. Potkonjak, "Exposure In Wireless Ad Hoc Sensor Networks", International Conference on Mobile Computing and Networking (MobiCom '01),pp. 139-150, Rome, Italy, July 2001. Best Student Paper Award.

  159. M. B. Srivastava, R. Muntz, M. Potkonjak, "Smart kindergarten: sensor-based wireless networks for smart developmental problem-solving environments", International Conference on Mobile Computing and Networking (MobiCom '01),pp. 132-138, Rome, Italy, July 2001. 

  160. S. Meguerdichian, S. Slijepcevic, V. Karayan, M. Potkonjak, "Localized Algorithms In Wireless Ad-Hoc Networks: Location Discovery and Sensor Exposure", MobiHOC 2001, Los Angeles, CA, October 2001.

  161. J.L. Wong, F. Koushanfar,  S. Meguerdichian , M. Potkonjak, "A Probabilistic Constructive Approach to Optimization Problems", ICCAD 2001, pp. 453-456, San Jose, CA, November 2001.

  162. J. L. Wong, S. Meguerdichian, F. Koushanfar, A. Morge, D. Petranovic, M. Potkonjak, "Probabilistic Control Search Strategies For Hardware And Software Optimization During Solution Space Exploration", PACO 2001, pp. 1-18, Moscow, October 2001.

  163. J.L. Wong, G. Qu, M. Potkonjak, "Power Minimization under QoS Constraints", International Packet Video Conference, April 2002.

  164. J.L. Wong, M. Potkonjak, "Search in Sensor Networks: Challenges, Techniques, and Applications", International Conference on Acoustics Speech and Signal Processing, pp. 3752 -3755, May 2002.

  165. J.L. Wong,  G. Veltri, M. Potkonjak, "Energy-efficient Data Multicast in Multi-Hop Wireless Networks", IEEE Workshop on Integrated Management of Power Aware Communications, Computing and Networking, May 2002.

  166. A. Srivastava, J. Sobaje, M. Potkonjak, M. Sarrafzadeh, "Optimal Node Scheduling of Effective Energy Usage in Sensor Networks", IEEE Workshop on Integrated Management of Power Aware Communications, Computing and Networking, May 2002. 

  167. S. Meguerdichian, M. Drinic, M. Potkonjak, “Watermarking Integer Linear Programming Solutions",  IEEE/ACM Design Automation Conference, pp. 8-13, June 2002.

  168. F. Koushanfar, J. L. Wong, J. Feng, M. Potkonjak, "ILP-based Engineering Change", IEEE/ACM Design Automation Conference, pp. 910-915, June 2002. 

  169. J.L. Wong, S. Megerian, M. Potkonjak, "Forward-Looking Objective Functions: Concepts and Applications in High Level Synthesis", IEEE/ACM Design Automation Conference , pp. 904-909, June 2002.

  170. F. Koushanfar, M. Potkonjak, A. Sangiovanni-Vincentelli, "Fault Tolerance in Wireless Ad-Hoc Sensor Networks", IEEE Sensors, Vol. 2, pp. 1491-1496, June 2002.

  171. S. Slijepcevic, V. Tsiatsis, S. Zimbeck, M. B. Srivastava, M. Potkonjak, "On Communication Security in Wireless Ad-Hoc Sensor Networks", 11th IEEE International Workshops on Enabling Technologies: Infrastructure for  Collaborative Enterprises, pp. 139-144, June 2002.

  172. R. Kastner, C. Hsieh, M. Potkonjak, M. Sarrafzadeh, "On the sensitivity of incremental algorithms for combinatorial auctions", Advanced Issues of E-Commerce and Web-Based Information Systems, pp. 81 -88, June 2002.

  173. J. Feng, F. Koushanfar, and M. Potkonjak, "System-Architectures for Sensor Networks Issues, Alternatives, and Directions", ICCD, special session on Sensor Networks, September 2002.    

  174. J. Feng, M. Potkonjak, "Power Minimization by Separation of Control and Data Radios", IEEE CAS Workshop on Wireless Communication and Networking, September 2002.    

  175. F. Koushanfar, S. Slijepcevic, M. Potkonjak, A. Sangiovanni-Vincentelli, "Error-Tolerant Multimodal Sensor Fusion", poster, IEEE CAS Workshop on Wireless Communications and Networking, September 2002.

  176. D. Kirovski, M. Drinic, M. Potkonjak, "Enabling Trusted Software Integrity", Architectural Support for Programming Languages and Operating Systems, October 2002.

  177. B. Shimanovsky, J. Feng, and M. Potkonjak, "Hiding Data in DNA", 5th Workshop on Information Hiding, October 2002. 

  178. J.L. Wong, G. Qu, M. Potkonjak, "An On-line Approach for Power Minimization in QoS Sensitive Systems", Asia South Pacific Design Automation Conference,  January 2003. 

  179. J. Feng, M. Potkonjak, "Real-time Watermarking Techniques for Sensor Networks", Security and Watermarking of Multimedia Contents, Santa Clara, California, January 2003. 

  180. M. Drinic, D. Kirovski, M. Potkonjak, "PPM Model Cleaning", Data Compression Conference, March 2003.

  181. S. Slijepcevic, S. Megerian M. Potkonjak, "Analysis of Location Error in Wireless Sensor Networks", 2nd International Workshop on Information Processing in Sensor Networks, pp. 593-608, April 2003.

  182. V. Bychkovskiy, S. Megerian, D. Estrin, M. Potkonjak. "Colibration: A Collaborative Approach to In-Place Sensor Calibration",  2nd International Workshop on Information Processing in Sensor Networks, April 2003.

  183. J.L. Wong, S. Megerian, M. Potkonjak, "Design Techniques for Sensor Appliances: Foundations and Light Compass Case Study", IEEE/ACM Design Automation Conference, June 2003.

  184. M. Drinic, D. Kirovski, M. Potkonjak, "Model Based Compression in Wireless Ad Hoc Networks", ACM SenSys 2003.

  185. F. Koushanfar, M. Potkonjak, A. Sangiovanni-Vincentelli, "On-line Fault-Detection of Sensor Measurements", IEEE Sensor, 2003.

  186. J. Feng, S. Megerian, M. Potkonjak, "Model based Calibration for Sensor Networks",  IEEE Sensor, 2003.

  187. G. Veltri, Q. Huang, G. Qu, M. Potkonjak, "Minimal and Maximal Exposure Path Algorithms for Wireless Embedded Sensor Networks", ACM SenSys 2003.

  188. Z. Zhang, Y. Fan, M. Potkonjak, J. Cong, "Gradual Relaxation Techniques for System Synthesis", International Conference on Computer Aided Design, 2003.

  189. F. Koushanfar, A. Davare, D. Nguyen, M. Potkonjak, A. Sangiovanni-Vincentelli. “Low Power Coordination in Wireless Ad-hoc Networks.” ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 475-480, August 2003.

  190. J. Feng, M. Potkonjak, "Sensor Calibration Using Nonparametric Statistical Characterization Of Error Models", IEEE Sensors 2004.

  191. J. Feng, M. Potkonjak, "Differential On-Line Sensor Calibration", IEEE Sensors 2004.

  192. F. Koushanfar, Alberto Sangiovanni-Vincentelli, Miodrag Potkonjak, "Error Models For Light Sensors By Non-Parametric Statistical Analysis Of Raw Sensor Measurements", IEEE Sensors 2004.

  193. J.L. Wong, M. Potkonjak, "Watermarking Multiple Constant Multiplications Solutions", Asilomar Conference on Signals, Systems and Computers, to appear, 2004.

  194. J.L. Wong, A. Davoddi, V. Khandelwal, A. Srivastava, M. Potkonjak, "Wire-length Prediction using Statistical and Probabilistic Techniques", International Conference on Computer Aided Design, to appear, 2004.

  195. J.L. Wong, M. Potkonjak, "Relative Generic Computational Forensic Techniques. Information Hiding Workshop", May 2004.

  196. J.L. Wong, R. Jafarri, M. Potkonjak, " Gateway Placement for Latency and Energy Efficient Data Aggregation". IEEE Workshop on Embedded Networked Sensors, to appear, 2004.

  197. J.L. Wong, F. Li, W. Liao, L. He, M.  Potkonjak, "Scheduling of Soft Real-Time Systems For Context-Aware Applications", DATE, to appear, 2005.

Patents

  1. L. Guerra, M. Potkonjak, J. Rabaey, "Behavioral Synthesis for Reconfigurable Datapath Structures", U.S. Patent, No. 5,502,645, March 26, 1996.

  2. S. Dey, M. Potkonjak, R. Roy, "High Level Synthesis for Partial Scan Testing", U.S. Patent No. 5,513,118, April 30, 1996.

  3. S. Dey, M. Potkonjak, "Non-Scan Design-for-Testability of RT-Level Data Paths", U.S. Patent No. 5,513,123, April 30, 1996.

  4. S. Dey, M. Potkonjak, R. Roy, "High-Level Circuit Design Synthesis Using Transformations", U.S. Patent No. 5,550,749, August 27, 1996.

  5. S. Dey, M. Potkonjak, S. Rothweiler, "Eliminating Retiming Bottlenecks to Improve Performance of Synchronous Sequential VLSI Circuits", U.S. Patent 5,553,000, September 3, 1996.