Instructor: Miodrag Potkonjak
Office Hours: M-W 11-12
Grading:
Homework 20%, Midterm 40%, Project 40%
I will cover the following topics:
- Design Flow and Synthesis Tools:
Case Study: Digital Camera
Case Study: Network Processor,
Case Study: Sensor Node, Implementation Technologies, Fabrics, Platforms, Business Models
- Physical Design:
Placement and floor planning techniques
Routing and Detail Routing
Data structures for Physical design
Layout migration
Symbolic design and compaction
Physical design planning
DRC, ERC and layout verification
Interaction between logic synthesis and layout
- Circuit and Interconnect-level simulation:
Interconnect parameter extraction and circuit model generation
Noise and cross-talk analysis
Timing models for interconnect
Timing analysis
Circuit-level delay and false path analysis
- Combinational logic optimization (area, timing, power):
Don't care methods, Technology Mapping
Sequential synthesis and optimization (including state encoding, retiming)
FPGA synthesis and optimization
- Behavioral Synthesis:
Resource Allocation, Scheduling, Assignment, Variable Assignment, Module Selection, Clock Selection, Template Matching and Operation Chaining, Partitioning, Transformations, Area, Time and Power Models, Partitioning for layout
Module generation and layout synthesis
Datapath control and memory system synthesis and optimization.
Estimation, use of libraries and synthesis environments
- Static Scheduling of Synchronous Data Flow:
Preemptive and Non-preemptive, Static and Dynamic,
Periodic and Aperiodic, Deterministic and Stochastic,
Single and Multiprocessor, PASS, Limitations
of the SDFG Models
- Hardware-Software Codesign
Co-design, Co-synthesis, Co-simulation, Co-specification, Co-verification, Architecture Selection, Mapping, Hardware Synthesis, Software Synthesis, Ptolemy, Formal Verification, Partitioning, ASIP, Berkeley's POLIS, CFSM,
Customized Operating Systems, Communication Mechanisms,
Code Generation, MIMOLA, Pattern Matching, Code Selection, Interface synthesis,
Issues for real-time systems and DSP,
ASIP synthesis
- Testing.
Fault models and fault simulation
Strategies for digital circuits and analog circuits.
Testability for digital circuits and analog circuits.
BIST & DFT schemes, Partial and boundary scan.
- Verification and Validation
Simulation, Emulation, Debugging,
Validation, Formal Verification,
Equivalence Checking, Model Checking,
Engineering Change
- Frameworks and CAD on the Internet
Middleware: inter-tool communication, databases and data management. Hardware design languages and user interface
- Low Power Design
Battery Technology, Rogone Plots, Pulsed Discharge,
Self-Power Chips, Fuel-Cells, Sources of Power Consumption,
CMOS Power Models, Digital Logic Power Models,
Architectural approaches to Power Minimization,
Circuit level Techniques, Software Power reduction techniques,
Power Prediction Techniques, Efficient I/O and Bus encoding,
Shutdown-based Techniques, Dynamic Variable Voltage Techniques,
Power Consumption in Disk-based Systems, Ultra Low power Systems,
Power Management techniques, Power minimization in Distributed Systems
- CAD Algorithms.
Force directed heuristics. Iterative Improvement.
Simulated Annealing, Mean-field, Taboo Search, Genetic Algorithms,
Linear Programming and ILP, Quadratic Programming, Semidefinite Programming.
Main Textbooks (only parts of each are relevant and
used):
- Giovanni De Micheli, "Synthesis and optimization of
digital circuits", New York : McGraw-Hill, 1994.
- "Design systems for VLSI circuits : logic synthesis
and silicon compilation", edited
by G. De Micheli, A. Sangiovanni-Vincentelli, P. Antognetti. Dordrecht ;
Boston : M. Nijhoff, 1987.
- Gary D. Hachtel, Fabio Somenzi. "Logic synthesis and
verification algorithms". Boston : Kluwer Academic Publishers, 1996.
- M. Sarrafzadeh, C.K. Wong. "An introduction to VLSI
physical design". New York : McGraw Hill, 1996.
- Naveed A. Sherwani. "Algorithms for VLSI physical design automation." Boston : Kluwer Academic Publishers, 1993.