PATENTS
1 Placement method for integrated circuit design using topo-clustering (6,851,099) Filed February 23, 2000, Granted February 1, 2005.
2 Methods for design optimization using logical and physical information (09,097,299) Filed June 1998, Granted March 2001.
3 System and method for concurrent placement of gates and associated wiring (6,385,760) Filed June 1998, Granted May 2002.
4 Placement method for integrated circuit design using topo-clustering (6,442,743) Filed June 12, 1998, Granted August 27, 2002.
5 Method and system for progressive clock tree or mesh construction concurrently with physical design (6,651,232) Filed November 5, 1998, Granted November 18, 2003.
1. M. Sarrafzadeh and D. T. Lee, Algorithmic Aspects of VLSI Layout, Lecture Notes Series on Computing, World Scientific; 1993 (edited book).
2. M. Sarrafzadeh and C. K. Wong, An Introduction to VLSI Physical Design, McGraw Hill, 1996 (authored book).
3. X. Yang, E. Bozorgzadeh, M. Sarrafzadeh and M. Wang, “Modern Standard-Cell Placement Techniques,” In Layout Optimization in VLSI Designs, Kluwer, 2001. (authored book chapter).
4. E. Bozorgzadeh, R. Kastner, S. Memik and M. Sarrafzadeh, “Strategically Programmable Systems,” The Computer Engineering Handbook, CRC Press, December 2001. (authored book chapter).
5. Srivastava, J. Sobaje, M. Potkonjak and M. Sarrafzadeh, Optimal Node Scheduling for Effective Energy Usage in Sensor Networks, System Level Power Optimization for Wireless Multimedia Communication, Kluwer, 2002.
6. E. Bozorgzadeh, A. Kaplan, R. Kastner, S. Memik and M. Sarrafzadeh, “Optimization for Reconfigurable Systems Using Hierarchical Abstraction,” Multi-level Optimization and VLSI CAD, J. Cong and J. R. Shinnerl (editors), Kluwer, Boston, 2002. (authored book chapter).
7. M. Sarrafzadeh, M. Wang and X. Yang, Modern Standard-Cell Placement Techniques, Kluwer, 2002. (authored book).
8. R. Kastner, A. Kaplan and M. Sarrafzadeh, Synthesis, Reconfigurable Systems, Kluwer, 2003 (authored book).
9. Foad Dabiri, Roozbeh Jafari, Ani Nahapetan, Majid Sarrafzadeh, Edited by Vojin Oklobdzija, Taylor & Francis/CRC Press "Light-weight Embedded Systems" to appear in Computer Engineering Handbook. (authored book chapter).
1. M. Sarrafzadeh and F. P. Preparata, “Compact Channel Routing of Multiterminal Nets,” Annals of Discrete Mathematics: Journal of Mathematics Studies, Vol. 25, April 1985, pp. 255-279.
2. K. Mehlhorn, F. P. Preparata and M. Sarrafzadeh “Channel Routing in Knock-Knee Mode: Simplified Algorithms and Proofs,” Algorithmica, Vol. 1, No.2, October 1986, pp. 213-221.
3. S. W. Hornick and M. Sarrafzadeh, “On Problem Transformability in VLSI,” Algorithmica, Vol. 2, No. 1, April 1987, pp. 97-111.
4. M. Sarrafzadeh, “Channel Routing in the Knock-Knee Mode is NP-Complete,” IEEE Transactions on Computer-Aided Design, Vol. CAD-6, No. 4, July 1987, pp. 503-506.
5. G. Bilardi and M. Sarrafzadeh, “Optimal VLSI Circuit for Discrete Fourier Transform,” Advances in Computing Research, Vol. 4, (F. P. Preparata ed.), JAI Press Inc., 1987, pp. 87-101.
6. M. Sarrafzadeh, “Channel Routing with Provably Short Wires,” IEEE Transactions on Circuits and Systems (Letters), Vol. CAS-34, No. 9, September 1987, pp. 1133-1135.
7. F.P. Preparata and M. Sarrafzadeh, “A Bottom-up Layout Technique Based on Two Rectangle Routing,” INTEGRATION: The VLSI Journal, Vol. 5, 1987, pp. 231-246.
8. M. Sarrafzadeh and D. T. Lee, “A New Approach to Topological Via Minimization,” IEEE Transactions on Computer-Aided Design, Vol. 8, No. 8, August 1989, pp. 890-900.
9. M. Brady and M. Sarrafzadeh “Stretching a Knock-knee Layout for Multilayer Wiring,” IEEE Transactions on Computers, Vol. 39, No. 1, January 1990, pp. 148-152.
10. C.C. Su and M. Sarrafzadeh, “Optimal Gate-matrix Layout of CMOS Functional Cells,” INTEGRATION: The VLSI Journal, January 1990, pp. 3-23.
11. J. M. Ho, M. Sarrafzadeh, G. Vijayan and C. K. Wong, “Pad Minimization for Planar Routing of Multiple Power Nets,” IEEE Transactions on Computer-Aided Design, Vol. 9, No. 4, April 1990, pp. 419-426.
12. K.F. Liao, D.T. Lee, and M. Sarrafzadeh, “Planar Subset of Multiterminal Nets,” INTEGRATION: The VLSI Journal, No. 1, Vol. 10, Sep. 1990, pp. 19-37.
13. M. Sarrafzadeh, “Area Minimization in a Three-sided Switchbox by Sliding the Modules,” IEEE Transactions on Computers, Vol. 39, No. 11, November 1990, pp. 1395-1398.
14. M. Sarrafzadeh and D. Zhou, “Global Routing of Short Nets in Two-Dimensional Arrays,” The International Journal of Computer Aided VLSI Design, (Special issue: Placement and Routing), Vol. 2, No. 2, 1990, pp. 197-211.
15. D. T. Lee, M. Sarrafzadeh and Y. F. Wu, “Minimum Cuts for Circular Arc Graphs,” SIAM Journal on Computing, Vol. 19, No. 6, December 1990, pp. 1041-1050.
16. J. M. Ho, M. Sarrafzadeh, G. Vijayan and C. K. Wong, “Layer Assignment for MultiChip Modules,” IEEE Transactions on Computer-Aided Design, Vol. 9, No. 12, December 1990, pp. 1272-1277.
17. C. Chiang, M. Sarrafzadeh and C. K. Wong, “Global Routing Based on Steiner Min-Max Trees,” IEEE Transactions on Computer-Aided Design, Vol. 9, No. 12, December 1990, pp. 1318-1325.
18. M. Sarrafzadeh, A. Katsaggelos and S. P. Kumar, “Parallel Architectures for Iterative Image Restoration,” A chapter in parallel algorithms and architectures for digital signal processing (M. Bayoumi, editor) Kluwer Academic Publishers, 1991, pp. 1-31.
19. M. Sarrafzadeh, “Tree Placement in Cascode-Switch Macros,” INTEGRATION: The VLSI Journal, Vol. 11, March 1991, pp. 127-139.
20. C. Chiang and M. Sarrafzadeh, “Wirability of Knock-knee Layouts with 45-degree Wires,” IEEE Transactions on Circuits & Systems, Vol. 38, No. 6, June 1991, pp. 613-624.
21. M. Sarrafzadeh and D. T. Lee, “Topological Via Minimization Revisited,” IEEE Transactions on Computers, Vol. 40, No. 11, November 1991, pp. 1307-1312.
22. K. F. Liao and M. Sarrafzadeh, “Boundary Single-Layer Routing with Movable Terminals,” IEEE Transactions on Computer-Aided Design, Vol. 10, No. 11, November 1991, pp. 1382-1391.
23. C. Chiang, M. Sarrafzadeh and C. K. Wong, “An Optimal Algorithm for Rectilinear Steiner Trees for Channels with Obstacles,” International Journal of Circuit Theory and Application, (John Wiley & Sons) Special issue: Fundamental methods in computer-aided circuit design, Vol. 19, No. 6, December 1991, pp. 551-563.
24. M. Sarrafzadeh and C. K. Wong, “Bottleneck Steiner Trees in the Plane,” IEEE Transactions on Computers, Vol. 41, No. 3, March 1992, pp. 370-374.
25. R. D. Lou, M. Sarrafzadeh and D. T. Lee, “An Optimal Algorithm for the Maximum Two-chain Problem,” SIAM Journal on Discrete Mathematics, Vol. 5, No. 2, May 1992, pp. 284-304.
26. N. Sherwani, Bo Wo and M. Sarrafzadeh, “Algorithms for Minimum-Bend Single Row Routing Problem,” IEEE Transactions on Circuits & Systems, (I: Fundamental Theory and Applications), Vol. 39, No. 5, May 1992, pp. 412-415.
27. J. Cong, A. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong, “Provably Good Performance Driven Global Routing,” IEEE Transactions on Computer-Aided Design, Vol. 11, No. 6, June 1992, pp. 739-752.
28. M. Sarrafzadeh and R. D. Lou, “Maximum k-Coverings of Weighted Transitive Graphs with Applications,” Algorithmica, Vol. 9, No. 1, pp. 84-100.
29. A. Katsaggelos, S.P. Kumar and M. Sarrafzadeh, “VLSI Architectures for Iterative Image Restoration Algorithms,” Journal of Circuits, Systems and Computers, Vol. 2, No. 3, September 1992, pp. 265-280.
30. R. D. Lou and M. Sarrafzadeh, ‘Circular Permutation Graph Family with Application,” Discrete Applied Mathematics, (special issue on: Discrete Algorithms and Complexity) Vol. 40, 1992, pp. 433-457.
31. R. D. Lou, K. F. Liao and M. Sarrafzadeh, “Planar Routing Around One Rectangle,” Journal of Circuits, Systems and Computers, (World Scientific Publishing), Vol. 2, No. 1, 1992, pp. 27-38.
32. Y. M. Huang and M. Sarrafzadeh, “A Parallel Algorithm for Minimum Dual Cover with Application to CMOS Layouts,” Journal of Circuits, Systems and Computers, (World Scientific Publishing) Vol. 1, No. 2, pp. 177-204.
33. M. Sarrafzadeh and C. K. Wong, “Hierarchical Steiner Tree Construction in Uniform Orientation,” IEEE Transactions on Computer-Aided Design, Vol. 11, No. 8, September 1992, pp. 1095-1103.
34. R. D. Lou, M. Sarrafzadeh, C. S. Rim, S. Masuda and K. Nakajima, “General Circular Permutation Layout,” Mathematical Systems Theory, Vol. 25, 1992, pp. 269-292.
35. Y. Sun and M. Sarrafzadeh, “Floorplanning by Graph Dualization: L-shaped Modules,” Algorithmica, Vol. 10, No. 6, 1993, pp. 429-456.
36. J. M. Ho, A. Suzuki and M. Sarrafzadeh, “An Exact Algorithm for Single-Layer Wire Length Minimization,” IEEE Transactions on Computer-Aided Design, Vol. 12, No. 1, January 1993, pp. 175-180.
37. C. Chiang, M. Sarrafzadeh and C. K. Wong, “An Algorithm for Exact Rectilinear Steiner Trees for Switchboxex with Obstacles,” IEEE Transactions on Circuits & Systems, (I: Fundamental Theory and Applications), Vol. 39, No. 6, pp. 446-455.
38. K. H. Yeap and M. Sarrafzadeh, “Floorplanning by Graph Dualization: Two-concave Rectilinear Modules,” SIAM Journal on Computing, Vol. 22, No. 3, June 1993, pp. 500-526.
39. Nancy Holmes, Naveed Sherwani and M. Sarrafzadeh, “Utilization of Vacant Terminals for Improved Over the Cell Routing,” IEEE Transactions on Computer-Aided Design, Vol. 12, No. 6, June 1993, pp. 780-792.
40. D. T. Lee and M. Sarrafzadeh, “Maximum Independent Set of a Permutation Graph in K Tracks,” International Journal of Computational Geometry and Application, Vol. 3, No. 3, September 1993, pp. 291-304.
41. K. H. Yeap and M. Sarrafzadeh, “Net-Regular Placement for High Performance Circuits,” International Journal of High Speed Electronics, Vol. 4, No. 3, October 1993.
42. R. D. Lou and M. Sarrafzadeh, “An Optimal Algorithm for the Maximum Three-Chain Problem,” SIAM Journal on Computing, Vol. 22, No. 5, October 1993, pp. 976-993.
43. K. H. Yeap and M. Sarrafzadeh, “A Unified Approach to Flooplan Sizing and Enumeration,” IEEE Transactions on Computer-Aided Design, Vol. 12, No. 12, December 1993, pp. 1858-1867.
44. J. D. Cho, M. Sarrafzadeh, M. Sriram and S. M. Kang, “High-Performance MCM Routing,” IEEE Design and TEST, December 1993, pp. 27-37.
45. M. Sarrafzadeh and D. T. Lee, “Restricted Track Assignment with Application,” International Journal of Computational Geometry and Application, Vol. 4, No. 1, 1994, pp. 53-68.
46. K. F. Liao, M. Sarrafzadeh and C. K. Wong, “Single-layer Global Routing,” IEEE Transactions on Computer-Aided Design, Vol. 13, No. 1, pp. 38-47.
47. J. D. Cho and M. Sarrafzadeh, “The Pin Redistribution Problem in Multi-Chip Modules,” Mathematical Programming, Series B, Vol. 63, February 1994, pp. 297-330.
48. C. Alpert, G. Robins, J. Cong, A. Kahng and M. Sarrafzadeh, “On the Minimum Density Interconnection Tree Problem,” VLSI Journal, Vol. 2, No. 2, February 1994, pp. 157-169.
49. J. D. Cho, S. Raje, K. F. Liao and M. Sarrafzadeh, “M 2R A New Multilayer Routing System for High-performance MCMs,” IEEE Transactions on Circuits and Systems, Vol. 41, No. 4, April 1994, pp. 253-255.
50. M. Sarrafzadeh, F. Wagner, D. Wagner and K. Weihe, “Wiring Knockknee Layouts: A Global Approach,” IEEE Transactions on Computers, Vol. 43, No. 5, May 1994, pp. 581-589.
51. A. Farrahi and M. Sarrafzadeh, “Complexity of the Lookup-Table Minimization Problem for FPGA Technology Mapping,” IEEE Transactions on Computer-Aided Design, Vol. 13, No. 11, November 1994, pp. 1319-1332.
52. C. Chiang, C. K. Wong, and M. Sarrafzadeh, “A Weighted Steiner Trees-Based Globar Router with Simultaneous Length and Density Minimization,” IEEE Transactions on Computer-Aided Design, Vol. 13, No. 12, December 1994, pp. 1461-1469.
53. K. H. Yeap and M. Sarrafzadeh, “Sliceable Floorplanning by Graph Dualization,” SIAM Journal on Discrete Mathematics, Vol. 8, No. 2, 1995, pp. 258-280.
54. M. Marek-Sadowska and M. Sarrafzadeh, “The Crossing Distribution Problem,” IEEE Transactions on Computer-Aided Design, Vol. 14, No. 4, pp. 423-433.
55. J. D. Cho and M. Sarrafzadeh, “A Buffer Redistribution Algorithm for High-Performance Clock Net Optimization,” IEEE Transactions on VLSI, Vol. 3, No. 1, March 1995, pp. 84-98.
56. S. Maddila and M. Sarrafzadeh, “The Discrete Warehouse Problem,” Theoretical Computer Science, April 1995, pp. 231-247.
57. S. Raje and M. Sarrafzadeh, “Scheduling with Multiple Voltages,” INTEGRATION: The VLSI Journal, Vol. 23, 1997, pp. 37-59.
58. M. Sarrafzadeh, D. Knol and G. Tellez, “A Delay Budgeting Algorithm Ensuring Maximum Flexibility in Placement,” IEEE Transaction on CAD, Vol. 16, No. 11, November 1997, pp. 1332-1341.
59. W.-L. Lin, C. K. Wong and M. Sarrafzadeh, "Floating Steiner Trees," IEEE Transactions on Computers, Vol. 47, No. 2, February 1998, pp. 197-211.
60. G. Tellez and M. Sarrafzadeh, “On Distance Preserving Rectilinear Steiner Trees,” VLSI Design, Vol. 7, No. 1, April 1998.
61. A. Farrahi, G. Tellez and M. Sarrafzadeh, “Exploiting Sleep Mode for Memory Partitions and Other Applications,” VLSI Design, Vol. 7, No. 3, pp. 271-287.
62. G. Tellez and M. Sarrafzadeh, “Minimal Buffer Insertion in Clock Trees with Skew and Slew Rate Constraints,” to appear in IEEE Transactions on Computer-Aided Design.
63. D.S. Chen, G. Yeap and M. Sarrafzadeh, “State Encoding of Finite State Machines for Low Power Design,” to appear in VLSI Design.
64. W.L. Lin and M. Sarrafzadeh, “On the Power of Re-Synthesis,” To appear in SIAM Journal on Computing.
65. S. Nicoloso and M. Sarrafzadeh, “Sum Coloring Problem on Interval Graphs,” to appear in Algorithmica.
66. A. Farrahi, D.T. Lee and M. Sarrafzadeh, “Two-Way and Multi-Way Partitioning of a Set of Intervals for Clique-Width Maximization,” to appear in Algorithmica.
67. J.D. Cho and M. Sarrafzadeh, “Mixed LP and Mincost Flow-based Four-bend Globar Routing in Two Dimensional Arrays,” IEEE Transactions on CAD, September 1998, pp. 793-802.
68. J.D. Cho, and S. Raje and M. Sarrafzadeh, “Fast Approximation Algorithms on Maxcut, k-coloring and k-color Ordering for VLSI Applications,” IEEE Transactions on Computers, Vol. 47, No. 11, November 1998, pp. 1253-1266.
69. J.D. Cho and M. Sarrafzadeh, Invited chapter in, Wiley Encyclopedia of Electrical and Electronics Engineering, (in the area of VLSI Circuit Layout), 1999.
70. K. Bazargan, S. Kim, and M. Sarrafzadeh, “Nostradamus: Floorplanner of Uncertain Designs,” IEEE Transactions on CAD, April 1999.
71. M. Enos, Scott Hauck and M. Sarrafzadeh, “Evaluation and Optimization of Replication Algorithms for Logic Replication,” IEEE Transactions on CAD, Vol. 18, No. 9, September 1999, pp. 1237-1248.
72. M. Wang, P. Banerjee and M. Sarrafzadeh, “Placement with Incomplete Data,” to appear in VLSI Design, Year 2000 special issue on Physical Design.
73. K. Bazargan and M. Sarrafzadeh, “Fast Template Based Placement for Reconfigurable Computing Systems,” special issue on Reconfigurable Computing of IEEE Design & Test, Jan-March 2000, pp. 68-83.
74. K. Bazargan, R. Kastner and M. Sarrafzadeh, “3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing System,” RSP’99 special issue of Journal of Design Automation for Embedded Systems (DAfES), April 2000.
75. A. Ranjan, K. Bazargan and M. Sarrafzadeh, “Fast Hierarchical Floorplanning with Congestion and Timing Control,” IEEE International Conference on Computer Design (ICCD) September 2000, pp. 357-362.
76. M. Wang and M. Sarrafzadeh, “Congestion Minimization during Placement,” IEEE Transactions on Computer-Aided Design (TCAD) Vol. 19, No. 10, October 2000, pp. 1140-1148.
77. K. Bazargan and M. Sarrafzadeh, “Fast Scheduling and Placement Methods for C to Hardware/Software Compilation,” SPIE International Symposium on Information Technologies, Vol. 4212, November 2000.
78. M. Breuer, F. Somenzi and M. Sarrafzadeh, “Fundamental CAD Algorithms,” IEEE Transactions on CAD (special issue on Electronic Design Automation at the Turn of the Century) Vol. 19, No. 12, December 2000, pp. 1449-1475.
79. M. F. Gorman and M. Sarrafzadeh, “An Application of Dynamic Programming to Crew Balancing at BNSF Railway,” International Journal of Services Technology and Management, Vol. 1, No. 2/3, 2000, pp. 174-187.
80. A. Nayak, M. Haldar, P. Banerjee, C. Chen and Majid Sarrafzadeh, “Power Optimization of Delay Constrained Circuits,” VLSI Design (Low-power System Design).
81. K. Bazargan, S. Ogrenci and M. Sarrafzadeh, “Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures,” Design Automation Conference (DAC), 2001, pp. 635-640.
82. A. Ranjan, K. Bazargan, S. Ogrenci and M. Sarrafzadeh, “Fast Floorplanning for Effective Prediction and Construction,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 2, April 2001, pp. 341-351.
83. Farrahi, C. Chen, A. Srivatsava, G. Tellez and M. Sarrafzadeh, “Activity Driven Clock Design for Low Power Circuits,” IEEE Transactions on CAD (TCAD), Vol. 20, No. 6, June 2001, pp. 705-714.
84. A. Srivastava, R. Kastner and M. Sarrafzadeh, “On the Complexity of Gate Duplication,” IEEE Transactions on CAD (TCAD), September 2001.
85. C. Chen, A. Srivatsava and M. Sarrafzadeh, “On Gate-Level Power Optimization Using Dual Supply Voltages,” IEEE Transactions on VLSI, Vol. 9, No. 5, Oct 2001, pp. 616-629.
86. A. Srivastava, C. Chen and M. Sarrafzadeh, “Timing Driven Gate Duplication in the
Technology Independent Stage,” IEICE Transactions on Fundamentals of Electronics,
Communications and Computer Sciences, Vol. E84-A, Nov. 2001, pp. 2673-2680.
87. X. Yang, E. Bozorgzadeh, M. Sarrafzadem and M. Wang, “Modern Standard-cell Placement Techniques,” in Optimization in VLSI Design: Floorplanning, Timing, and Layout (D.Z. Du and B. Lu, editors), January 2002.
88. X. Yang, R. Kastner and M. Sarrafzadeh, “Congestion Estimation During Top-down Placement,” IEEE Transactions on CAD (TCAD), Vol. 21, No. 1, January 2002, pp. 72-80.
89. C. Chen, X. Yang and M. Sarrafzadeh, “Predicting Potential Performance for Digital Circuits,” IEEE Transactions on CAD, Vol. 21, No. 3, March 2002, pp. 253-262.
90. M. Sarrafzadeh, E. Bozorgzadeh, R. Kastner and S. Ogrenci, “SPS: A Strategically Programmable System,” A chapter in the Computer Engineering Handbook, CRC Press, 2002.
91. C. Chen and M. Sarrafzadeh, “Simultaneous Voltage Scaling and Gate Sizing for Low Power Design,” IEEE Transactions on Circuits and Systems (Part II), Vol. 49, No. 6, June 2002, pp. 400-408.
92. R. Kastner, E. Bozorgzadeh and M. Sarrafzadeh, “Pattern Routing: Use and Theory for Increasing Predictability and Avoiding Coupling,” IEEE Transactions on CAD, Vol. 21, No. 7, July 2002, pp. 777-790.
93. S. Ghiasi, A. Srivastava, X. Yang and M. Sarrafzadeh, “Optimal Energy Aware Clustering in Sensor Networks,” SENSORS Journal, Vol. 2, Issue 7, July 2002, pp. 258-269.
94. C. Chen, E. Bozorgzadeh, A. Srivatsava and M. Sarrafzadeh, “Budget Management and Its Applications,” Algorithmica, Vol. 34, No. 3, July 2002, pp. 261-275.
95. R. Kastner, A. Kaplan, S. Ogrenci Memik and E. Bozorgzadeh, “Instruction Generation for Hybrid Reconfigurable Systems,” ACM Transactions on Design Automation of Embedded Systems (TODAES) Vol. 7, No. 4, October 2002.
96. A. Srivastava, E. Kursun, and M. Sarrafzadeh, “Predictability in RT-Level Designs,” special issue on Low Power IC Designs in the Journal of Circuits, Systems and Computers.
97. E. Bozorgzadeh, A. Kaplan, R. Kastner, and S. Ogrenci and M. Sarrafzadeh, “Multi-Level Optimization in Reconfigurable Computing Systems,” Multilevel Optimization and VLSI CAD, Kluwer Academic Publishers, Boston, 2002.
98. A. Srivastava E. Kursun and M. Sarrafzadeh, “Predictability in RT-Level Designs,”Proceedings of the Journal of Circuits, Systems and Computers, Special Issue on Low Power IC Design, (JCSC) August 2002, Vol. 11, No. 4, pp. 323-332.
99. S. Ghiasihafezi, A. Srivastava, X. Yang and M. Sarrafzadeh, “Optimal Energy Aware Clustering in Sensor Networks,” SENSORS Journal, July 2002, Vol.2, Issue 7, pp. 258-269.
100.S. E. Kursun and M. Sarrafzadeh, “Predictability in RTL-Designs,” To Appear in Journal of Circuits, Systems and Computers (JCSC) Special Issue on Low Power IC Designs.
101.A. Srivastava, J. Sobaje, M. Potkonjak and M. Sarrafzadeh, “Optimal Node Scheduling for Effective Energy Usage in Sensor Networks,” A chapter in System-Level Power Optimization for Wireless Multimedia Communication, Kluwer Academic Publishers, 2002.
102.X. Yang, B.K. Choi and M. Sarrafzadeh, “Wirelength Estimation based on Rent Exponents of Partitioning and Placement,” to appear in IEEE Transactions on CAD.
103.S. Ogrenci, A. Katsaggelos and M. Sarrafzadeh, “FPGA Analysis and Implementation of an Iterative Image Restoration,” IEEE Transactions on Computers, Vol. 52, No. 3, March 2003, pp. 390-399.
104.X. Yang, B.K. Choi and M. Sarrafzadeh, “Routability-Driven Whitespace Allocation for Fixed-Die Standard-Cell Placement,” IEEE Transactions on Computer-Aided Design (TCAD) Vol. 22, April 2003.
105.E. Bozorgzadeh, R. Kastner and M. Sarrafzadeh, “Creating and Exploiting Flexibility in Rectilinear Steiner Trees,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD) Vol. 22, No. 5, May 2003.
106.X. Yang, M. Wang, R. Kastner, S. Ghiasi and M. Sarrafzadeh, “Congestion Reduction During Placement with Provably Good Approximation Bound,” ACM Transactions on Design Automation of Electronic Systems (TODAES) Vol. 8, No. 3, July 2003, pp. 316-333.
107.S. Ghiasi, A. Nahapetian and M. Sarrafzadeh, “An Optimal Algorithm for Minimizing Runtime Reconfiguration Delay,” To Appear in ACM Transactions on Embedded Computing Systems (TECS).
108.A. Srivastava, C. Chen and M. Sarrafzadeh, “Timing Driven Gate Duplication in Technology Independent Phase,” in Special Section on VLSI Design and CAD Algorithms of the IEEE Transactions, January 2004.
109.E. Bozorgzadeh, S. Ogrenci Memik, X. Yang and M. Sarrafzadeh, “Routability-Driven Packing: Metrics and Algorithms for Cluster-based FPGAs,” Journal of Circuits, Systems and Computers (JCSC) Vol. 13, No. 1, February 2004, pp. 77-100.
110.S. Ghiasi, A. Nahapetian and M. Sarrafzadeh, “An Optimal Algorithm for Minimizing Runtime Reconfiguration Delay,” ACM Transactions on Embedded Computing Systems (TECS) Vol. 3, No 2, pp. 237-256, May 2004.
111.E. Bozorgzadeh, S. Ghiasi, A. Takahashi and M. Sarrafzadeh, “Optimal Integer Delay Budget Assignment on Directed Acyclic Graphs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) Vol. 23, No 8, August 2004, pp. 1184-1199.
112.S. Ghiasi, H. J. Moon, A. Nahapetian and M. Sarrafzadeh, “Collaborative and Reconfigurable Object Tracking,” Kluwer Journal of Supercomputing, Vol. 30, No 3, December 2004, pp. 213-238.
113.S. Ghiasi, K. Nguyen, E. Bozorgzadeh and M. Sarrafzadeh, “Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System,” to appear in the Journal on Applied Signal Processing (EURASIP)Volume 42, Issue 1, Jan 2006, Pages 43 - 55.
114.S. Ghiasi, A. Nahapetian, H. J. Moon and M. Sarrafzadeh, “Reconfiguration in Network of Embedded Systems: Challenges and Adaptive Tracking Case Study,” Journal of Embedded Computing (JEC), Vol. 1, No 1, 2005, pp. 147-166.
115. S. Memik, E. Bozorgzadeh, R. Kastner and M. Sarrafzadeh, “A Scheduling Algorithm for Optimization and Planning in High-level Synthesis,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 10, No. 1, January 2005.
116.S. Memik, A. Srivastava, B. K. Choi and M. Sarrafzadeh, “On Effective Slack Management in Post-Scheduling Phase,” IEEE Transactions on Computer Aided-Design of Integrated Circuits and Systems, Vol. 24, No. 4, April 2005.
117. A. Srivastava, R. Kastner, C. Chen and M. Sarrafzadeh, “Timing Driven Gate Duplication,” Proceedings of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI) January 2004, pp. 42-51.
118. Soheil Ghiasi, Elaheh Bozorgzadeh, Po-kuan Huang, Majid Sarrafzadeh, “A Unified Theory of Timing Budget Management”, to appear in IEEE Transactions on Computer-Aided Design (TCAD).
119.Roozbeh Jafari, Foad Dabiri, Philip Brisk, Majid Sarrafzadeh, “Reconfigurable Fabric Vest for Fatal Hear Disease Prevention” to appear in Journal of Embedded Computing (JEC).
120.Philip Brisk, Foad Dabiri, Roozbeh Jafari, and Majid Sarrafzadeh "Optimal Register Sharing for High-Level Synthesis of SSA-Form Programs" IEEE Transactions on CAD (TCAD), vol 25 no. 5, pp 772-779, May 2006.
121.Adaptive Electrocardiogram Feature Extraction on Distributed Embedded Systems, Roozbeh Jafari, Hyduke Noshadi, Soheil Ghiasi, Majid Sarrafzadeh, IEEE Transactions on Parallel and Distributed Systems special issue on High Performance Computational Biology (TPDS), vol. 17, no. 8, pp 1-11, August 2006.
122. Roozbeh Jafari, Foad Dabiri, Ani Nahapetian, Majid Sarrafzadeh, “An Efficient Placement and Routing Technique for Fault-tolerant Distributed Embedded Computing,” to appear in ACM Transactions on Embedded Computing Systems (TECS).
123. Foad Dabiri, Roozbeh Jafari, Ani Nahapetian, Majid Sarrafzadeh, “Lightweight Embedded Systems,” to appear in [Book Chapter] Computer Engineering Handbook, Edited by Vojin Oklobdzija, Taylor and Francis/CRS Press.
124. F. P. Preparata and M. Sarrafzadeh, “Channel Routing of Nets of Bounded Degree,” Proceeding of the VLSI: Algorithms and Architectures (P. Bertolazzi and F. Luccio ed.), North-Holland, 1984, pp. 189-203. (Invited Paper)
125. G. Bilardi and M. Sarrafzadeh, “Optimal Discrete Fourier Transform in VLSI,” Proceeding of the VLSI: Algorithms and Architectures (P. Bertolazzi and F. Luccio ed.), North-Holland, 1984, pp. 79-89.
126.M. Sarrafzadeh, “On the Complexity of the General Channel Routing Problem in the Knock-Knee Mode,” Proceedings of the 20th Annual Conference on Information Sciences and Systems, Princeton, NJ, March 1986, pp. 161-164.
127.M. Sarrafzadeh, “Layout Stretching to Ensure Wirability,” Proceeding of the 21st Annual Conference on Information Sciences and Systems, (with M. L. Brady), Johns Hopkins, March 25-28, 1987, pp. 588-593.
128.Y. M. Huang and M. Sarrafzadeh, “A Parallel Algorithm for Minimum Dual-Cover with Application to CMOS Layout," Proceedings of the 1988 International Conference on Parallel Processing.
129.M. Sarrafzadeh, “Multilayer Routing in Sea-of-Gates,” Proceeding of the IFIP Workshop on Physical Design of Sea of Gates in VLSI, W. Germany, August 1988.
130. R. D. Lou and M. Sarrafzadeh, “General Circular Permutation Layout,” Proceedings of the 1988 Allerton Conference, October 1988, pp. 1136-1137.
131.R.D. Lou, K. F. Liao and M. Sarrafzadeh, “Planar Routing Around a Rectangle,” Proceeding of the 1988 International Computer Symposium, Taipei, Taiwan.
132.A. Katsaggelos, S. Kumar and M. Sarrafzadeh, “Parallel Processing Architectures for Iterative Image Restoration,” Proceedings of the 1989 IEEE International Conference on ASSP, Glasgow, Scotland, pp. 2544-2547.
133.C. Chiang and M. Sarrafzadeh, “Using 45-degree Wires to Ensure Wirability,” Proceeding of the 20th International Conference on Combinatorics, Graph Theory and Computing, Boca Raton, Florida, February 1989.
134.M. Sarrafzadeh and D. Zhou, “Theoretical Aspects of Global Routing,” Proceeding of the 20th International Conference on Combinatorics, Graph Theory and Computing, Boca Raton, Florida.
135.G. Bilardi, S. Hornick and M. Sarrafzadeh, “Optimal VLSI Architecture for Multidimensional DFT,” Proceedings of the 1989 ACM Symposium on Parallel Algorithms and Architectures, NM, June 18-21, 1989, pp. 265-272.
136.C. Chiang, M. Sarrafzadeh and C. K. Wong, “A Powerful Global Router: Based on Steiner Min-Max Trees,” Proceedings of the International Symposium on Computer-Aided-Design (ICCAD-89), Santa Clara, CA, November 1989, pp. 2-5.
137. R.D. Lou, D.T. Lee and M. Sarrafzadeh, “An Optimal Algorithm for the Maximum Two-chain Problem,” Proceedings of the First ACM SIAM Conference on Discrete Algorithms, San Francisco, January 1990, pp. 149-158.
138.R. D. Lou and M. Sarrafzadeh, “Circular Permutation Family of Graphs,” Proceedings of the International Workshop on Discrete Algorithms and Complexity, Fukuoka, Japan, November 1989, pp. 107-114.
139.A. Katsaggelos, S. Kumar and M. Sarrafzadeh, “Parallel Architecture for an Iterative Image Restoration Algorithms,” Proceedings of the IEEE International Symposium on Circuits and System (ISCAS) May 1990, pp. 2605-2608. (Invited Paper)
140.Y. Sun and M. Sarrafzadeh, “Floorplanning by Graph Dualization: L-shaped Modules,” Proceedings of the IEEE International Symposium on Circuits and System (ISCAS) May 1990, pp. 2845-2848.
141.R. D. Lou and M. Sarrafzadeh, “Maximum k-Coverings of Weighted Transitive Graphs with Applications,” Proceedings of the IEEE International Symposium on Circuits and System (ISCAS) May 1990, pp. 332-335. (Invited Paper)
142.M. Nag and M. Sarrafzadeh, “A Parallel Algorithm for Two-Layer Wiring,” Proceedings of the 1990 International Conference on Parallel Processing.
143.K. F. Liao and M. Sarrafzadeh, “Vertex-disjoint Trees in Planar Graphs,” Proceeding of the 16th International Workshop on Graph-Theoretic Concepts in Computer Science (WG-90), with K.F. Liao, Berlin, West Germany, June 1990.
144.J. M. Ho, A. Suzuki and M. Sarrafzadeh, “An Exact Algorithm for Single Layer Wire-Length Minimization,” Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD-90), with J.M. Ho and A. Suzuki, Santa Clara, CA, November 1990, pp. 424-427.
145.R.D. Lou and M. Sarrafzadeh, “An Efficient Algorithm for the Maximum k-chain Problem,” Proceedings of the 1990 Allerton Conference, with R.D. Lou, pp. 315-323.
146.N. Holmes, N. Sherwani and M. Sarrafzadeh, “New Algorithms for Over-the-Cell Channel Routing Using Vacant Terminals,” Proceedings of the 1991 IEEE Design Automation Conference (DAC'91), with N. Holmes and N. Sherwani, pp. 126-131.
147.J. D. Cho and M. Sarrafzadeh, “The Pin Redistribution Problem in Multi-Chip Modules,” Proceedings of ASIC'91: Fourth Annual IEEE International ASIC Conference and Exhibit, with J. D. Cho, Rocehster, NY, September 23-27, 1991, pp. 9-2-1 to 9-2-4.
148.K. F. Liao, C. K. Wong and M. Sarrafzadeh, “Single Layer Global Routing,” Proceedings of ASIC'91: Fourth Annual IEEE International ASIC Conference and Exhibit, with K. F. Liao and C. K. Wong, Rocehster, NY, September 23-27, 1991, pp. 14-4-1 to 14-4-4.
149.J. Cong, A. Kahng, G. Robins and M. Sarrafzadeh, “Performance Driven Global Routing for Cell Based IC's,” Proceedings of the IEEE International Conference on Computer Design (ICCD), October 14-16, 1991, pp. 170-173.
150.N. Holmes, N. Sherwani and M. Sarrafzadeh, “Algorithms for Three-Layer Over-the-Cell Channel Routing,” Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD-91), with N. Holmes and N. Sherwani, Santa Clara, CA, November 1991, pp. 428-431. (Distinguished Paper)
151.M. Marek-Sadowska and M. Sarrafzadeh, “The Crossing Distribution Problem,” Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD-91) with M. Marek-Sadowska, Santa Clara, CA, November 1991, pp. 528-531. (Distinguished Paper)
152.M. Sarrafzadeh and D. T. Lee, “Maximum Independent Set of a Permutation Graph in k Tracks,” Proceedings of The Second Annual International Symposium on Algorithm, with D. T. Lee, Taipei, Taiwan, December 1991.
153.K.H. Yeap and M. Sarrafzadeh, “A Theorem on Slicability,” Proceeding of the Second Great Lakes Computer Science Symposium, with K. H. Yeap, November 1991, Kalamazoo, MI.
154.K.H. Yeap and M. Sarrafzadeh, “Graph Dualization: 2-concave Modules are Necessary and Sufficient,” Proceedings of the 1991 Allerton Conference, with K. H. Yeap.
155.J. Cong, A. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong, “Provably Good Performance Driven Global Routing,” with J. Cong, A. Kahng, G. Robins, and C. K. Wong, Proceedings of the IEEE International Symposium on Circuits and System (ISCAS-92), pp. 739-752.
156.B. Wu, N. Sherwani and M. Sarrafzadeh, “On Minimum Bend Single Row Routing,” Proceedings of the IEEE International Symposium on Circuits and System (ISCAS-92), with Bo Wu and N. Sherwani, pp. 29-32.
157.C. Chiang, M. Sarrafzadeh and C. K. Wong, “An Optimal Algorithm for Exact Rectilinear Steiner Trees For Switchbox with Obstacles,” Proceedings of the IEEE International Symposium on Circuits and System (ISCAS-92), with C. Chiang and C. K. Wong, pp. 9- 12.
158.N. Holmes, N. Sherwani and M. Sarrafzadeh, “Over-the-Cell Channel Routing for High-Performance Circuits,” Proceedings of the 1992 IEEE Design Automation Conference (DAC'92), with N. Holmes and N. Sherwani, pp. 600-603.
159.N. Holmes, N. Sherwani and M. Sarrafzadeh, “Over-the-Cell Routing for New Cell Models,” Proceedings of the 1992 IEEE Design Automation Conference (DAC'92) with N. Holmes and N. Sherwani, pp. 604-607.
160.J.D. Cho, K. F. Liao and M. Sarrafzadeh, “Multilayer Routing Algorithm for High Performance MCMs,” Proceedings of ASIC'92: Fifth Annual IEEE International ASIC Conference and Exhibit, with J. D. Cho and K. F. Liao, Rochester, NY, September 1992, pp. 226-229.
161.D.S. Chen and M. Sarrafzadeh, “A Wire-length Minimization Algorithm for Single-layer Layouts,” Proceeding of the International Conference on Computer-Aided Design (ICCAD-92) with D.S. Chen.
pp. 390-393.
162.D.T. Lee and M. Sarrafzadeh, “Restricted Track Assignment with Application,” Proceedings of the International Symposium on Algorithms and Computation, with D. T. Lee, Nagoya, Japan, December 1992.
163.F. Wagner, D. Wagner, K. Weihe and M. Sarrafzadeh, “Wiring Knock-knee Layouts: A Global Approach,” Proceedings of the International Symposium on Algorithms and Computation, Nagoya, Japan, December 1992.
164.K. H. Yeap and M. Sarrafzadeh, “An Integrated Algorithm designed for Optimal Floorplan Sizing and Enumeration,” Proceedings of the 1993 European Design Automation Conference, Paris, France, February 1993, pp. 29 – 33.
165.G. Robins, J. Cong, A. B. Kahng and M. Sarrafzadeh, “Minimum Density Interconnection Trees,” Proceeding of the 1993 International Symposium on Circuits and Systems (ISCAS-93) pp 1865-1868.
166.S.Raje and M. Sarrafzadeh, “GEM: A Geometric Algorithm for Scheduling,” Proceeding of the 1993 International Symposium on Circuits and Systems (ISCAS-93) May 1993.
167.M. Sriram, S. Kang, J.D. Cho, S. Raje and M. Sarrafzadeh, “Crosstalk-Minimum Layer Assignment,” Proceedings of the Custom Integrated Circuits Conference, San Diego, CA, May 1993, pp. 29.7.1 - 29.7.4.
168.J.D. Cho and M. Sarrafzadeh, “A Buffer Redistribution Algorithm for High-Speed Clock Routing,” Proceedings of the 1993 IEEE Design Automation Conference (DAC'93) pp. 537-543. (Best paper award)
169.M. Sriram, S. Kang, J.D. Cho, S. Raje and M. Sarrafzadeh, “A Multilayer Assignment Algorithm for Interference Minimization,” Proceedings of the 4th ACM-SIGDA Physical Design Workshop, Lake Arrowhead, CA, April 19-21, 1993, pp. 63-67.
170.M. Sarrafzadeh, “Transforming an Arbitrary Floorplan into a Sliceable One,” Proceedings of the International Conference on Computer-Aided Design (ICCAD-93) pp. 386-389.
171.A. Farrahi and M. Sarrafzadeh, “On the Lookup-table Minimization Problem for FPGA Technology Mapping,” Proceedings of the Workshop on FPGAs, Berkeley, CA, February 13-15, 1994.
172.J.D. Cho and Y. Kajitani and M. Sarrafzadeh, “New Approximation Results on Graph Matching and Related Problems,” Proceedings of the 20th International Workshop (WG-1994) Vol. 903, pp. 343-358.
173.A. Farrahi and M. Sarrafzadeh, “FPGA Technology Mapping for Power Minimization,” Proceedings of the Workshop on Field Programmable Logic and Applications (FPL'94) Prague, CZ, September 7-9, pp. 66-77.
174.J. D. Cho and Salil Raje and M. Sarrafzadeh, “New Approximation Results for Maxcut and Related Problems,” Proceedings of the 2nd Annual European Symposium on Algorithms (ESA'94) Utrecht, Netherlands, September 1994, pp. 148-158.
175.G. Tellez and M. Sarrafzadeh, “Clock Period Constrained Minimal Buffer Insertion in Clock Trees,” Proceedings of the International Conference on Computer-Aided Design, ICCAD-94; pp. 219-223.
176.W. Lin, C. K. Wong and M. Sarrafzadeh, “The Reproducing Placement Problem with Application,” Proceedings of the International Conference on Computer-Aided Design, ICCAD-94; pp. 686-689.
177.W. Lin and M. Sarrafzadeh, “A Linear Arrangement Problem with Applications,” Proceedings of the 1995 International Symposium on Circuits and Systems (ISCAS) April 1995, Seattle, WA, pp. 57-60.
178.D. S. Chen, G. Yeap and M. Sarrafzadeh, “State Encoding of Finite State Machines for Low Power Design,” Proceedings of the 1995 International Symposium on Circuits and Systems (ISCAS) Seattle, WA, April 1995.
179.G. Tellez and M. Sarrafzadeh, “On Rectlinear Distance Preserving Steiner Trees,” Proceedings of the 1995 International Symposium on Circuits and Systems (ISCAS) Seattle, WA , April 1995, pp. 163-166.
180.A. Farrahi and G. Tellez and M. Sarrafzadeh, “Memory Segmentation to Exploit Sleep Mode Operation,” Proceedings of the 32nd Design Automation Conference (DAC) June 1995, pp. 36-41.
181.E. Frank and S. Raje and M. Sarrafzadeh, “Constrained Register Allocation in Bus Architectures,” Proceeding of the 1995 Design Automation Conference (DAC).
182.A. Farrahi and M. Sarrafzadeh, “Interval Graph Partitioning for Clique-width Maximization,” Proceedings of the 26th International Conference on Combinatorics, Graph Theory and Computing, Boca Raton, FL, March 1995.
183.S. Raje and M. Sarrafzadeh, “Variable Voltage Scheduling,” Proceedings of the 1995 International Symposium on Low Power Design,” Dana Point Resort, Dana Point, CA April 23-26, 1995.
184.A. Farrahi and M. Sarrafzadeh, “System Partitioning to Maximize Sleep Time,” Proceedings of the International Conference on Computer-Aided Design (ICCAD) San Jose, CA, November 1995, pp. 452-455.
185.A. Farrahi, G. Tellez and M. Sarrafzadeh, “Activity-Driven Clock Design for Low Power Circuits,” Proceedings of the International Conference on Computer-Aided Design (ICCAD) San Jose, CA, Novemeber 1995, pp. 62-65.
186.D. Knol, G. Tellez and M. Sarrafzadeh, “A Graph-Based Delay Budgeting Algorithm for Large Scale Timing-Driven Placement Problems,” Proceedings of the 5th ACM SIGDA Physical Design Workshop, Reston, VA, April 15-17, 1996.
187.D.S. Chen and M. Sarrafzadeh, “An Exact Algorithm for Low-Power Gate Resizing,” Proceedings of the 1996 Design Automation Conference (DAC-96).
188.D.S. Chen and M. Sarrafzadeh, “Cube-Embedding Based State Encoding,” Proceedings of the Asia South Pacific DAC (ASP-DAC97) Tokyo, Japan, January 1997.
189.J. Crenshaw and M. Sarrafzadeh, “An Accurate Behavioral Level Power Estimator,” Proceedings of the ED & TC 1997, Paris, France, March 1997.
190.D. Knol, G. Tellez and M. Sarrafzadeh, “A Solution to Large Scale Timing-Driven Placement Problems,” Proceedings of the 1997 Design Automation Conference (DAC-97).
191.A. Farrahi and M. Sarrafzadeh, “TDD: Fast Technology Mapping with Accurate Prediction,” Proceedings of the ASIC'97: Annual IEEE International ASIC Conference and Exhibit.
192.M. Enos, S. Hauck and M. Sarrafzadeh, “Logic Partitioning with Replication,” Proceedings of the International Conference on Computer-Aided Design (ICCAD 97).
193.M. Wang and M. Sarrafzadeh, “NRG: Global and Detailed Placement,” Proceedings of the International Conference on Computer-Aided Design (ICCAD 97).
194.P. Banerjee, S. Roy and M. Sarrafzadeh, "Partitioning Sequential Circuits for Low Power, Low Power Circuit Partitioning," Proceeding of the 11th International Conference on VLSI Design.
195.J. Crenshaw and M. Sarrafzadeh, “Low-Power Driven Scheduling and Binding,” Proceedings of the 1997 Great Lakes Symposium on VLSI, Lafayette, LA, February 19-21, 1998.
196.K. Bazargan, S. Kim and M. Sarrafzadeh, “Nostradamus: Floorplanner of Uncertain Designs,” Proceedings of the 1998 International Symposium on Physical Design (ISPD 98).
197.M. Wang, P. Banerjee and M. Sarrafzadeh, “Placement with Incomplete Data,” Proceedings of the 1998 Design Automation Conference (DAC-98).
198.P. Prabhakaran, J. Crenshaw, P. Banerjee and M. Sarrafzadeh, “Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization,” Proceedings of the 1999 VLSI Design Conference, Goa, India, January 1999.
199.J. Crenshaw, P. Prabhakaran, P. Banerjee and M. Sarrafzadeh, “An Incremental Floorplanner,” Proceeding of the 1998 Great Lakes Symposium on VLSI, March 4-6, Ann Arbor, MI.
200.S. Raje and M. Sarrafzadeh, “Scheduling with Multiple Voltages under Resource Constraints,” Proceedings of the 1999 International Symposium on Circuits and Systems (ISCAS) pp. 350-353, May 30-June 2, 1999, Miami, FL.
201.M. Sarrafzadeh and T. Takahashi, “A Fast Algorithm for Routability Testing,” Proceedings of the 1999 International Symposium on Circuits and Systems (ISCAS) May 30 - June 2 1999, Miami, FL.
202.M. Wang and M. Sarrafzadeh, “Congestion Minimization During Placement,” Proceedings of the 1999 International Symposium on Physical Design (ISPD 99) Monterey, CA.
203.A. Ranjan, K. Bazargan and M. Sarrafzadeh, “Floorplannig 1000 times Faster,” Proceedings of the System Level Interconnect Prediction (SLIP 99).
204.M. Sarrafzadeh and M. Wang, “Can Fast Algorithms Be Used as Good Predictors?” Proceedings of the System Level Interconnect Prediction (SLIP 99). (Position Statement)
205.K. Bazargan, R. Kastner and Majid Sarrafzadeh, “3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems,” Proceedings of the 10th IEEE International Workshop on Rapid System Prototyping, Sheraton Sandkey, Clearwater, FL June 16-18, 1999.
206.K. Bazargan and M. Sarrafzadeh, “Fast Online Placement for Reconfigurable Computing Systems,” Proceedings of the IEEE FCCM: Symposium on Field Programmable Custom Computing Machines, Napa Valley, CA, April 21-23, 1999.
207.C. Chen and M. Sarrafzadeh, “Slack Equalization Algorithm: Precise Slack Distribution for Low-Level Synthesis and Optimization,” Proceedings of the International Workshop on Logic Synthesis (IWLS) Lake Tahoe, CA, June 1999, pp. 190-192.
208.ICCAD 1999 full day tutorial, “Modern Physical Design: Algorithm, Technology and Methodology.”
209.C. Chen and M. Sarrafzadeh, “Power Reduction by Simultaneous Voltage Scaling and Gate Sizing,” Proceedings of the ASP-DAC 2000, Yokohama, Japan, pp. 333-338.
210.C. Chen and M. Sarrafzadeh, “An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages,” Proceedings of the ICCD, October 1999, Austin, TX, pp. 222-2327.
211.M. Sarrafzadeh and M. Wang, “Interaction Among Cost Function During Placement,” Proceedings of the International Conference on VLSI and CAD, Seoul, Korea, October 26-29, 1999. (Invited Paper)
212.R. Kastner, K. Bazargan and M. Sarrafzadeh, “Physical Design of Reconfigurable Computing Systems with Firm Macros,” Proceedings of the Workshop on Reconfigurable Computing (WoRC’99), October 1999.
213.C. Chen and M. Sarrafzadeh, “Provably Good Algorithm for Low Power Consumption with Dual Supply Voltages,” to appear in Proceedings of the International Conference on Computer-Aided Design, ICCAD, November 7-10, 1999, pp. 76-79.
214.S. Ogrenci, K. Bazargan and M. Sarrafzadeh, “Image Analysis and Partitioning for FPGA Implementation of Image Restoration,” Proceedings of the IEEE Workshop on Signal Processing Systems, 2000, pp. 346-355.
215.M. Wang and M. Sarrafzadeh, “Modeling and Minimization of Routing Congestion,” Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC 2000) China.
216.M. Wang, S. Lim, J. Cong and Majid Sarrafzadeh, “Multi-way Partitioning Using Bi-partition Heuristics,” Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC 2000) China.
217.A. Farrahi, D. Hathaway, M. Wang and M. Sarrafzadeh, "Quality of EDA CAD Tools: Definitions, Metrics and Directions," Proceedings of ISQED 2000, March, San Jose, CA. (Invited paper)
218.S. Ogrenci, A. Katsaggelos and M. Sarrafzadeh, “FPGA Analysis and Implementation of Image Restoration,” Poster presentation at the ACM International Symposium on Field Programmable Gate Arrays (FPGA 2000) Monterey, CA, February 10-11, 2000.
219.K. Bazarga, A.Ranjan and M. Sarrafzadeh, “Fast and Accurate Estimation of Floorplans in Logic/High-level Synthesis,” Proceedings of the 2000 Great Lakes Symposium on VLSI (GLSVLSI 2000) Chicago, IL, March 2-4, 2000, pp. 95-100.
220.M. Wang, X. Yang, K. Eguro and M. Sarrafzadeh, “Multi-Center Congestion Minimization During Placement,” Proceedings of the International Symposium on Physical Design (ISPD) April 2000, pp. 147-152.
221.M. Wang, X. Yang, K. Eguro and M. Sarrafzadeh, “A Snap-On Placement Tool,” Proceedings of the International Symposium on Physical Design (ISPD) April 2000, pp. 153-158.
222.J. Cong and M. Sarrafzadeh, “Incremental Physical Design,” Proceedings of the International Symposium on Physical Design (ISPD 2000). (Invited paper)
223.K. Bazargan, R. Kastner, S. Ogrenci and M. Sarrafzadeh, “A C to Hardware/Software Compiler,” Proceedings of the IEEE Symposium on Field Programmable Custom Computing Machines (IEEE: FCCM) Napa Valley, CA, April 21-23, 2000.
224.A. Nayak, P. Banerjee, C. Chen and M. Sarrafzadeh, “Power Optimization Issues in Dual Voltage Design,” ICDA 2000 (part of World Computer Congress 2000) Beijing, China, August 21-25, 2000, pp. 99-105.
225.A. Srivatsava, R. Kastner, M. Sarrafzadeh, “Gate Duplication for Performance Optimization,” Proceedings of the International Workshop on Logic Synthesis (IWLS) Los Angeles, CA, June 2000.
226.A. Srivastava, R. Kastner and M. Sarrafzadeh, “Complexity Issues in Gate Duplication,” Proceedings of the International Workshop on Logic Synthesis (IWLS) June 2000.
227.A. Ranjan, K. Bazargan and M. Sarrafzadeh, “Fast Hierarchical Floorplanning with Congestion and Timing Control,” Proceedings of the International Conference on Computer Design (ICCD), Austin, TX, September 17-20, 2000, pp. 357-362.
228.A. Nayak, M. Haldar, P. Banerjee, C. Chen and M. Sarrafzadeh, “Power Optimization of Delay Constrained Circuits,” Proceedings of the 2000 ASIC/SOC Conference, Washington D.C., pp. 305-309.
229.R. Kastner, E. Bozorgzadeh and M. Sarrafzadeh, “Coupling Aware Routing,” Proceedings of the IEEE International ASIC/SOC Conference, Washington, D.C., September 2000.
230.A. Srivatsava, R. Kastner and M. Sarrafzadeh, “Timing Driven Gate Duplication: Complexity Issues and Alogrithms,” Proceedings of the International Conference on Computer-Aided Design (ICCAD) San Jose, CA, November 2000, pp. 447-450.
231.C. Chen, X. Yang and M. Sarrafzadeh, “Potential Slack: An Effective Metric of Combinational Circuit Peformance,” Proceedings of the International Conference on Computer-Aided Design (ICCAD) San Jose, CA, November 2000, pp. 198-201.
232.M. Wang, X. Yang, K. Eguro and M. Sarrafzadeh, “Dragon2000: Placement of Industrial Circuits,” Proceedings of the International Conference on Computer-Aided Design (ICCAD) November 2000, pp. 260-263.
233.R. Kastner, E. Bozorgzadeh and M. Sarrafzadeh, “Predictable Routing,” Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD) November 2000.
234.A. Kahng and M. Sarrafzadeh, “Modern Physical Design,” Tutorial from the International Conference on Computer-Aided Design (ICCAD) 2000. (Tutorial)
235.J. Cong, O. Coudert and M. Sarrafzadeh, “Incremental CAD,” Embedded Tutorial from the International Conference on Computer-Aided Design (ICCAD) 2000. (Tutorial)
236.K. Bazargan, S. Ogrenci and M. Sarrafzadeh, “A Fast Scheduling and Placement Method for C to Hardware/Software Compilation,” Reconfigurable Techniques for Computing, Part of Photonics East Conference, Boston, MA, November 5-8.
237.S. Ogrenci, K. Bazarga and M. Sarrafzadeh, “Image Analysis and Partitioning for FPGA Mapping,” IEEE Workshop on Signal Processing Systems (SiPS) Lafayette, LA, 2000.
238.A. Srivatsava, C. Chen and M. Sarrafzadeh, “Timing Driven Gate Duplication in Technology Independent Phase,” Proceedings of the ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC) Yokohama, Japan, Jan 31-Feb 2, 2001.
239.E. Bozorgzadeh, S. Ogrenci and M. Sarrafzadeh, “R-Pack: Routability-Driven Packing for Cluster-Based FPGAs,” Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC) Yokohama, Japan, Jan 31-Feb 2, 2001.
240.A. Ranjan, A. Srivatsava, V. Karnam and M. Sarrafzadeh, “Layout Aware Retiming,” Proceedings of the ACM/SIGDA Great Lakes Symposium on VLSI: GLSVLSI, March 2001.
241.Tutorial with Xilinx et al on “Field Programmable Devices,” DAC 2001. (Tutorial)
242.X. Yang, E. Bozorgzadeh and M. Sarrafzadeh, “Wirelength Estimation Based on Rent Exponents of Partitioning and Placement,” Proceedings of System-Level Interconnect Prediction (SLIP) Sonoma, CA, March 31-April 1, 2001.
243.S. Ogrenci, E. Bozorgzadeh, R. Kastner and M. Sarrafzadeh, “Strategically Reconfigurable Gate Arrays,” Proceedings of the Reconfigurable Architecture Workshop (RAW) April 2001.
244.R. Kastner, E. Bozorgzadeh and M. Sarrafzadeh, “An Exact Alogrithm for Coupling-Free Routing,” Proceedings of the ACM/IEEE International Symposium on Physical Design (ISPD) April 2001.
245.S. Ogrenci Memik, E. Bozorgzadeh, R. Kastner and M. Sarrafzadeh, “SPS: Strategically Programmable Systems,” Proceedings of the Reconfigurable Architecture Workshop (RAW) San Francisco, CA, April 2001.
246.M. Sarrafzadeh, E. Bozorgzadeh, R. Kastner and A. Srivastava, “Design and Analysis of Physical Design Algorithms,” Proceedings of the ACM/SIGDA International Symposium on Physical Design (ISPD) April 2001.
247.X. Yang, R. Kastner and M. Sarrafzadeh, “Congestion Estimation During Top-down Placement,” Proceedings of the International Symposium on Physical Design 2001 (ISPD) Sonoma County, CA, April 1-4, 2001, pp. 164-169.
248.M. Sarrafzadeh and students, “Fundamental Graph Algorithms in Physical Design,” Proceedings of the International Symposium on Physical Design 2001 (ISPD) Sonoma County, CA, April 1-4, 2001. (Invited Paper)
249.A. Srivatsava, C. Chen and M. Sarrafzadeh, “Exact Algorithm for Modifying Buffer Trees Using Buffer Duplication in a Delay Optimization Perspective,” Proceedings of the ACM/SIGDA International Workshop on Logic Synthesis (IWLS) June 2001, pp. 179-184.
250.E. Bozorgzadeh, R. Kastner and M. Sarrafzadeh, “Creating and Exploiting Flexibility in Steiner Trees,” Proceedings of the ACM/IEEE Design Automation Conference (DAC) Las Vegas, NV, June 2001, pp. 195-198.
251.P. Schaumont, I. Verbawhede, K. Keutzer and M. Sarrafzadeh, “A Quick Safari Through the Reconfigurable Jungle,” Las Vegas Convention Center, June 2001, pp. 172-177. (Invited Paper)
252.K. Bazargan, S. Ogrenci, and M. Sarrafzadeh, “Integrated Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures,” Proceedings of the IEEE/ACM Design Automation Conference (DAC) Las Vegas Convention Center, June 2001, pp. 635-640. (Best Paper Award Nomination)
253.A. Srivastava, R. Kastner and M. Sarrafzadeh, “On the Complexity of Gate Duplication,”
Proceedings of the IEEE Transactions on Computer-Aided Design (TCAD) September 2001, Vol. 20, pp. 1170-1176.
254.A.B. Kahng, R. Kastner, S. Mantik, M. Sarrafzadeh and X. Yang, “Studies of Timing Structural Properties for Early Evaluation of Circuit Design,” (SASIMI) Japan, October 2001.
255.R. Kastner, S. Ogrenci-Memik, E. Bozorgzadeh and M. Sarrafzadeh, “Instruction Generation for Hybrid Reconfigurable Systems,” Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD) San Jose, CA, November 2001.
256.X. Yang, R. Kastner and M. Sarrafzadeh, “Congestion Reduction During Placement Based on Integer Programming,” Proceedings of the International Conference on Computer-Aided Design (ICCAD) San Jose, CA, November 2001, pp. 573-576.
257.S. Ogrenci-Memik, E. Bozorgzadeh, R. Kastner and M. Sarrafzadeh, “A Super-Scheduler for Embedded Reconfigurable Systems,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) San Jose, CA, November 2001.
258.C. Chen and M. Sarrafzadeh, “Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis,” 2002.
259.C. Chen, A. Srivastava and M. Sarrafzadeh, “Budget Management and its Applications,” ALGORITHMICA, 2002, pp. 261-275.
260.S. Ogrenci-Memik, A. Srivatsava and M. Sarradzadeh, “Design under Uncertainties,” Proceedings of the International Symposium on Circuits & Systems (ISCAS 2002); special session on COMPUTATIONAL GRAPH THEORY FOR COMPUTER AND COMMUNICATION SYSTEMS, Phoenix, AZ.
261.E. Bozorgzadeh, S. Ogrenci-Memik, R. Kastner and M. Sarrafzadeh, “Pattern Selection in Programmable Systems,” Poster Presentation at the International Symposium of Field Programmable Gate Arrays (FPGA) Monterey, CA, February 2002.
262.X. Yang, B.K. Choi and M. Sarrafzadeh, “Routability Driven White Space Allocation for Fixed-die Standard-cell Placement,” ISPD 2002, San Diego, CA, April 2002, pp. 42-47.
263.S. Ogrenci-Memik, A. Srivatsava, E. Kursun and M. Sarrafzadeh, “Alogrithmic Aspects of Uncertainty Driven Scheduling,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) Scottsdale, AZ, May 2002.
264.A. Srivastava, J. Sobaje, M. Potkonjak and M. Sarrafzadeh, “Optimal Node Scheduling
for Effective Energy Usage in Sensor Networks,” Proceedings of the IEEE Workshop on Integrated
Management of Power Aware Communications, Computing and Networking, May 2002.
265.R. Kastner, C. Hsieh, M. Potkonjak and M. Sarrafzadeh, “On the Sensitivity of Incremental Algorithms for Combinatorial Auctions,” UCLA Computer Science Department Technical Report 020000, January 2002, Proceedings of the IEEE International Workshop on Advanced Issues of E-Commerce & Web-Based Information Systems (WECWIS) June 2002.
266.E. Bozorgzadeh, S. Ogrenci-Memik, R. Kastner and M. Sarrafzadeh, “Pattern Selection: Customized Block Allocation for Domain-Specific Programmable Systems,” Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) June 2002.
267.E. Bozorgzadeh, S. Ogrenci-Memik, R. Kastner and M. Sarrafzadeh, “Customized Block Allocation for Domain-Specific Programmable Systems,” Poster presentation at the 2002 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) Las Vegas, NV, June 24-27, 2002.
268.A. Srivatsava and M. Sarrafzadeh, "Predictability Driven Binding,” Proceedings of the IEEE/ACM International Workshop on Logic & Synthesis (IWLS), New Orleans, LA, June 4-7, 2002.
269.E. Kursun, A. Srivastava, S. Ogrenci-Memik and M. Sarrafzadeh, “Early Evaluation Techniques for Low Power Binding,” Proceedings of the ISLPED'02: ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) Monterey, CA, August 2002.
270.C. Chen, C. Kang, and M. Sarrafzadeh, “Activity-Sensitive Clock Tree Construction for Low Power,” Poster presentation at the ISLPED'02: ACM/IEEE International Symposium on Low Power Electronics and Design, Monterey, CA, August 2002.
271.. Yang, B.K. Choi and M. Sarrafzadeh, “Standard-Cell Placement Tool for Designs with High Row Utilization,” Proceedings of the International Conference on Computer Design (ICCD) Freiburg, Germany, September 16-18, 2002.
272.P. Brisk, A. Kaplan, R. Kastner, and M. Sarrafzadeh, “Instruction Generation and Regularity Extraction for Reconfigurable Processors,” Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES) Grenoble, France, October 8-11, 2002.
273.S. Ghiassi, K. Nguyen, and M. Sarrafzadeh, “A General Framework for Tracking Objects in a Multi-Camera Environment,” Proceedings of the Third International Workshop on Digital and Computational Video (DCV '02) Florida, November 2002, pp. 200-204.
274.A. Srivastava and M. Sarrafzadeh, “Predictability: Definition Analysis and Optimization,” Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD) November 2002.
275.X. Yang, B.K. Choi and M. Sarrafzadeh, “Timing-Driven Placement using Design Hierarchy Guided Constraint Generation,” Proceedings of the International Conference on Computer-Aided Design (ICCAD) November 2002.
276.R. Jafari, H. Fan and M. Sarrafzadeh, “A Programmable System with Quick Reconfiguration,” Proceedings of DesignCon, San Jose, CA, January 2003.
277.S. Ghiasi and M. Sarrafzadeh, “Optimal Reconfiguration Sequence Management,” Proceedings of the Asia South Pacific Design Automation Conference (ASPDAC) January 2003, pp. 359-365.
278.Kaplan, M. Sarrafzadeh and R. Kastner, “High-Level Data Communication Optimization for Reconfigurable Systems,” Proceedings of the Workshop on Software Support for Reconfigurable Systems (SSRS), in conjunction with the International Symposium on High-Performance Computer Architecture (HPCA) February 2003.
279.S. Ghiasi, K. Nguyen, E. Bozorgzadeh and M. Sarrafzadeh, “On Computation and Resource Management in an FPGA-based Computing Environment,” A poster at the International Symposium on Field-Programmable Gate Arrays (FPGA) February 2003, page 243.
280.S. Kumar, S. Ghiasi, M. Srivastava, “Dynamic Adaptation of Networked Reconfigurable Systems,” Proceedings of the Workshop on Software Support for Reconfigurable Systems (SSRS) February 2003.
281.S. Ghiasi, H. J. Moon and M. Sarrafzadeh, “Collaborative and Reconfigurable Object Tracking,” Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) Las Vegas, NV, June 2003, pp.13-20.
282.R. Jafari, He. Fan and M. Sarrafzadeh, “Micro-Sequencer Approach Speeds Reconfiguration,” COTS Journal, June 2003.
283.Kaplan, P. Brisk, and R. Kastner, “Data Communication Estimation and Reduction for Reconfigurable Systems,” Proceedings of the 40th Design Automation Conference (DAC) June 2003.
284.E. Bozorgzadeh, S. Ghiasi, A. Takahashi and M. Sarrafzadeh, “Optimal Integer Delay Budgeting on Directed Acyclic Graphs,” Proceedings of the ACM/IEEE Design Automation Conference (DAC) June 2003, Anaheim, CA, pp. 920-925.
285.B.K. Choi. H. Xu, and M. Sarrafzadeh, “Flow-Based Cell Moving Algorithm for Desired Cell Distribution,” Proceedings of the International Conference on Computer Aided Design (ICCAD) 2003.
286.S. Ghiasi, H. J. Moon and M. Sarrafzadeh, “Improving Performance and Quality through Hardware Reconfiguration: Potentials and Adaptive Object Tracking Case Study,” Proceedings of the Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia) Newport Beach, CA, October 2003, pp. 149-155.
287.Srivastava, S. Ogrenci-Memik, B.K. Choi and M. Sarrafzadeh, “Achieving Design Closure Through Delay Relaxation Parameter,” Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD) San Jose, CA, November 2003.
288.S. Ghiasi, E. Bozorgzadeh, K. Nguyen and M. Sarrafzadeh, “On Computation and Resource Management in Networked Embedded Systems,” Proceedings of the International Conference on Parallel and Distributed Computing and Systems, Marina Del Rey, CA, November 2003, pp. 445-451.
289.S. Ghiasi, K. Nguyen and M. Sarrafzadeh, “Profiling Accuracy Latency Characteristics of Collaborative Object Tracking Applications,” Proceedings of the International Conference on Parallel and Distributed Computing and Systems, Marina Del Rey, CA, November 2003, pp. 694-701.
290.P. Brisk, A. Kaplan and M. Sarrafzadeh, “Parallel Analysis of the Rijndael Block Cipher,” Proceedings of the International Conference on Parallel and Distributed Computing and Systems (IASTED-PDCS) Marina Del Rey, CA, November 3-5, 2003.
291.A. Nahapetian, S. Ghiasi and M. Sarrafzadeh, “Task Scheduling on Heterogeneous Resources with Heterogeneous Reconfiguration Costs,” Proceedings of the Parallel and Distributed Computing and Systems (PDCS): Special Session on Synthesis for Programmable System, November 2003, pp. 916-921.
292. C. Chen, et al., "Reconfigurable Fabric: An Enabling Technology for Pervasive Medical Monitoring,” Proceedings of the Communication Networks and Distributed Systems Modeling and Simulation Conference (CNDS) San Diego, CA, January 2004.
293.F.C. Chen, F. Dabiri, R. Jafari, E. Kursun, V. Raghunathan, T. Schoellhammer, D. Sievers, D. Estrin, G. Reinman, M. Sarrafzadeh, M. Srivastava, B. Wu and Y. Yang, “Reconfigurable Fabric: An Enabling Technology for Pervasive Medical Monitoring,” Proceedings of the Communication Networks and Distributed Systems Modeling and Simulation Conference (NDS) San Diego, CA, January 18-24 2004.
294.P. Brisk and M. Sarrafzadeh, “Framework and Design Methodology for a Compiler that Compresses Code Using Echo Instructions,” Proceedings of the 2nd Workshop on Optimization for DSP and Embedded Systems (ODES-2) March 2004.
295.P. Brisk and M. Sarrafzadeh, “Framework and Design Methodology of a Compiler that Compresses Code using Echo Instructions,” ODES-2: Proceedings of the 2nd Workshop on Optimizations for DSP and Embedded Systems, The Sheraton Hotel and Conference Center, Palo Alto, CA, March 21, 2004.
296.S. Ghiasi, E. Kursun and M. Sarrafzadeh, “Transistor Level Budgeting for Power Optimization,” Proceedings of the International Symposium on Quality Electronic Design (ISQED) 2004, San Jose, CA, pp. 116-121.
297.T. Taghavai, S. Ghiasi, A. Ranjan, S. Raje and M. Sarrafzadeh, “Innovate or Perish: FPGA Physical Design,” International Symposium on Physical Design (ISPD) Phoenix, AZ, April 2004, pp. 148-155.
298.Chiang, B.K. Choi and M. Sarrafzadeh, “Routing Resources Consumption on M-arch and X-arch,” Proceedings of the International Symposium on Circuits and Systems (ISCAS) Vancouver, Canada, May 23-26, 2004.
299.P. Brisk and M. Sarrafzadeh, “Framework and Design Methodology for a Compiler that Compresses Code Using Echo Instructions,” Proceedings of the Southern California Workshop on Parallel and Distributed Processing and Architecture, May 2004.
300.P. Brisk, A. Kaplan and M. Sarrafzadeh, “Area Efficient Instruction Set Synthesis for Reconfigurable System-on-Chip Designs,” Proceedings of the 41st Design Automation Conference (DAC) June 7-11, 2004, pp. 395-400.
301.E. Bozorgzadeh, S. Ghiassi, A. Takahashi and M. Sarrafzadeh, “Incremental Timing Budget Management in Programmable Systems,” Proceedings of the International Conference on Embedded and Reconfigurable Systems and Architecture, July 2004.
302.P. Brisk, A. Nahapetian and M. Sarrafzadeh, “Instruction Selection for Compilers that Target Architectures with Echo Instructions,” Proceedings of the 8th International Workshop on Software and Compilers for Embedded Systems (SCOPES) September 2004.
303.R. Jafari, F. Dabiri and M. Sarrafzadeh, “Reconfigurable Fabric Vest for Fatal Heart Disease Prevention,” Proceedings of the 3rd International Workshop on Ubiquitous Computing for Pervasive Healthcare Applications in conjunction with UbiComp'04 (UbiHealth) Nottingham, UK, September 2004.
304.S. Ghiasi, E. Bozorgzadeh, S. Choudhury and M. Sarrafzadeh, “A Unified Theory for Timing Budget Management,” Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD) November 2004, pp. 653-659.
305.T. Taghavi, X. Yang, BK Choi, M. Wang and M. Sarrafzadeh, “Dragon 2005: Large Scale Mixed-Sized Placement Tool,” Proceedings of the International Symposium on Physical Design (ISPD) Placement Design Contest 2005.
306.R. Kastner, P. Brisk, A. Kaplan, F. Brewer and M. Sarrafzadeh, “Physically Aware Data Communication Optimization for Hardware Synthesis,” Proceedings of the International Workshop on Logic and Synthesis (IWLS 2005).
307.R. Jafari, F. Dabiri, P. Brisk and M. Sarrafzadeh, “Adaptive and Fault Tolerant Medical Vest for Life-Critical Medical Monitoring,” Proceedings of the 20th ACM Symposium on Applied Computing (SAC) Santa Fe, NM, March 13-17, 2005.
308.R. Jafari, F. Dabiri, B.K. Choi and M. Sarrafzadeh, “Efficient Placement and Routing in Grid-Based Networks,” Poster presentation at the 20th ACM Symposium on Applied Computing (SAC) Santa Fe, NM, March 2005.
309.P. Brisk, J. Macbeth, F. Dabiri and M. Sarrafzadeh, “Polynomial-Time Graph Coloring Register Allocation,” Proceedings of the International Workshop on Logic and Synthesis (IWLS 2005).
310.P. Brisk, J. Macbeth, A. Nahapetian and M. Sarrafzadeh, "A Dictionary Construction Technique for Code Compression Systems with Echo Instructions,” Proceedings of the Conference on Languages Compilers and Tools for Embedded Systems (LCTES) 2005.
311.R. Jafari, S. Ogrenci-Memik and M. Sarrafzadeh, “Quick Reconfiguration in Clustered Micro-Sequencer,” Proceedings of the 12th Reconfigurable Architectures Workshop (RAW) in conjunction with the International Computer Performance and Dependability Symposium (IPDS) Denver, CO, April 4-5,2005.
312.R. Jafari, F. Dabiri, P. Brisk and M. Sarrafzadeh “CustoMed: A Power Optimized Customizable and Mobile Medical Monitoring and Analysis System,” Proceedings of the ACM HCI Challenges in Health Assessment Workshop in conjunction with Computer Human Interaction (CHI) Portland, OR, April 2005.
313.R. Kastner, W. Gong, X. Hao, F. Brewer, A. Kaplan, P. Brisk and M. Sarrafzadeh, “Physically Aware Data Communication Optimization for Hardware Synthesis,” Proceedings of the International Workshop on Logic and Synthesis (IWLS) June 2005.
314.R. Jafari, A. Encarnacao, A. Zahoory, F. Dabiri, H. Noshadi and M. Sarrafzadeh, “Wireless Sensor Networks For Health Monitoring,” Proceedings of the Second ACM/IEEE International Conference on Mobile and Ubiquitous Systems (Accepted as a Short Paper) San Diego, CA, July 2005.
315.R. Jafari, F. Dabiri and M. Sarrafzadeh, “An Efficient Placement and Routing Technique for Fault-tolerant Distributed Embedded Computing,” Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, Hong Kong, China, August 2005.
316.Ryan Kastner, Wenrui Gong§, Xin Hao§, Forrest Brewer§, Adam Kaplan†, Philip Brisk† and Majid Sarrafzadeh , “Layout Driven Data Communication Optimization for High-level Synthesis”, DATE 2006.
317.Ani Nahapetian, Foad Dabiri, Majid Sarrafzadeh, "Energy Minimization and Reliability for Wearable Medical Applications" International Conference on Parallel Processing (ICPP), August 2006.
318. Gao, Tia. Tammara Massey, Will Bishop, Daniel Bernstein, Leo Selavo, Alex Alm, David White, and Majid Sarrafzadeh. "Integration of Triage and Biomedical Devices for Continuous, Real-Time, Automated Patient Monitoring". 3rd IEEE-EMBS International Summer School and Symposium on Medical Devices and Biosensors (ISSS-MDBS 2006). Boston, MA. September 2006.
319.Gao, Tia. Tammara Massey, "An Integrated, Wireless Triage System and Biomedical Devices for Continuous, Real-Time, Automated Patient Monitoring". 3rd IEEE-EMBS International Summer School and Symposium on Medical Devices and Biosensors (ISSS-MDBS 2006). Boston, MA. September 2006.
320.Taraneh Taghavi and Majid Sarrafzadeh, "Blockage Oriented Placement,"IEEE Electronic. Design rocess Workshop, 2006.
321.Ryan Kastner, Wenrui Gong, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh, Xin Hao, and Forrester Brewer, “*Layout Driven Data Communication Optimization for High Level Synthesis”*,/Design, Automation and Test in Europe Conference (DATE),/March 2006.
322. Philip Brisk, Foad Dabiri, Jamie Macbeth, and Majid Sarrafzadeh. “Polynomial Time Graph Coloring Register Allocation,” 14th International Workshop on Logic and Synthesis.
323. Taraneh Taghavi, Xiaojian Yang, BK Choi, Maogang Wang, and Majid Sarrafzadeh, “Dragon2006: Blocakage-Aware Congestion-Controlling Mixed-Sized Placer,” in Proc. of International Symposium on Physical Design (ISPD), 2006.
324. Taraneh Taghavi, Soheil Ghiasi, and Majid Sarrafzadeh, Routhing Algorithms: Architecture Driven Rerouthing Enhancement for FPGAs,” in Proc. International Symposium on Circuits and Systems (ISCAS), 2006.
325. Tammara Massey, Tia Gao, Matt Welsh, Jonathan Sharp, and Majid Sarrafzadeh. “The Design of a Decentralized Electronic Triage System.” American Medical Informatics Association (AMIA). Washington, DC, November 2006.
326. Majid Sarrafzadeh, Foad Dabiri, Roozbeh Jafari, Tammara Massey, and Ani Nahapetan. “Low Power Light-Weight Embedded Systems.” International Symposium on Low Power Electronics and Design (ISLPED), Tegernsee, Germany, October 2006.
327. Foad Dairi, Ani Nahapetan, and Majid Sarrafzadeh. “General Delay Budgeting on Directed Acyclic Graphs with Applications in CAD.” Electronic Notes in Discrete Mathematics 27, pp. 95-96, 2006, Short Communication.
328. Roozbeh Jafari, Hyduke Noshadi, Soheil Ghiasi, Majid Sarrafzadeh, “Adaptive Medical Feature Extraction for Resource Constrained Distributed Embedded Systems.” The first IEEE International Workshop on Pervasive and Ubiquitous Health Care (UbiCare) in conjunction with PerCom, March 2006, Pisa, Italy.
329. Roozbeh Jafari , Devin L. Jindrich, V. Reggie Edgerton, Majid Sarrafzadeh, “CMAS: Clinical Movement Assessment System for Neuromotor Disorders,” IEEE Biomedical Circuits and Systems Conference (BioCAS), November-December 2006, London, UK.
330. Philip Brisk, Majid Sarrafzadeh, “Interference Graphs for Procedures in Static Single Information Form are Interval Graphs.” SCOPES 2007, Acropolis, Nice, France. April, 2007.
331.Tutorial, “Medical Embedded Systems,” IESS 2007 Conference, Irvine, CA May 29 – June 1, 2007.
332. Taraneh Taghavi and Majid Sarrafzadeh, “Heirarchical Concurrent Congestion and Wirelength Estimation in the Presence of IP Blocks,” IEEE Computer Society Annual Symposium on VLSI 2007. Porto Alegre, Brazil, May 2007.
333. Roozbeh Jafari, V. Reggie Edgerton and Majid Sarrafzadeh, “Reliability in Light-weight Medical Monitoring Platforms,” BSN2007 – Body Sensing Networks 4th International Workshop on Wearable and Implantable Body Sensor Networks. Aachen, Germany, March 26 – 28, 2007.
334. C.K. Lin, David Jea, Foad Dabiri, Tammara Massey, Robert Tan, Majid Sarrafzadeh, Mani Srivastava, Peter Schulam, Jacob Schmidt, “The Development of an In-vivo Active Pressure Monitoring System,” BSN2007 – Body Sensing Networks 4th International Workshop on Wearable and Implantable Body Sensor Networks. Aachen, Germany, March 26 – 28, 2007.
335. Ani Nahapetian, Paolo Lombardi, Andrea Acquaviva, Luca Benini, Majid Sarrafzadeh, “Dynamic Reconfiguration in Sensor Networks with Regenerative Energy Sources,” Design Automation and Test Europe (DATE), April 2007.
336. Foad Dabiri, Roozbeh Jafari, Ani Nahapetian, Majid Sarrafzadeh, “A Unified Optimal Voltage Selection Methodology for Low-power Systems,” International Symposium on Quality Electronic Design (ISQED), March 2007.
337. Taraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh, “System Level Estimation of Interconnect Length in the Presence of IP Blocks,” International Symposium on Quality Electronic Design (ISQED), March 2007.
338. Taraneh Taghavi, Foad Dabiri, Ani Nahapetian, Majid Sarrafzadeh, “Congestion Prediction,” Workshop on System Level Interconnect Prediction (SLIP), March 2007.
339. S. Nakatake, Z. Karimi, T. Taghavi, and M. Sarrafzadeh, “Block Placement to Ensure Channel Routability” to appear in ACM Great Lakes Symposium on VLSI (GLSVLSI), 2007.