Adam Kaplan Current Information Teaching Research / Publications Research Interests Practical Simulation of Tens/Hundreds of Active Processor Cores Scalable Interconnect Design For Chip Multiprocessors Dynamic Management Policies for Non-Uniform Cache Architectures 3D Integration Via Vertical Die-Stacking Publications Books [B1] Ryan Kastner, Adam Kaplan and Majid Sarrafzadeh, "Synthesis Techniques and Optimizations for Reconfigurable Systems", Kluwer Academic Publishers, November 2003, ISBN 1-4020-7598-3 (order) Book Chapters [BC1] Elaheh Bozorgzadeh, Adam Kaplan, Ryan Kastner, Seda Ogrenci Memik, and Majid Sarrafzadeh, "Optimization for Reconfigurable Systems Using Hierarchical Abstraction", Multi-level Optimization and VLSI CAD, J. Cong and J.R. Shinnerl (editors), Kluwer Academic Publishers, Boston, 2002 Journal Publications [J1] Ryan Kastner, Adam Kaplan, Seda Ogrenci Memik, Elaheh Bozorgzadeh, "Instruction Generation for Hybrid Reconfigurable Systems", ACM Transactions on Design Automation of Electronic Systems, October 2002 Refereed Conference and Workshop Publications [C1] Philip Brisk, Adam Kaplan, Ryan Kastner, and Majid Sarrafzadeh, "Instruction Generation and Regularity Extraction for Reconfigurable Processors", International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), October 2002 [C2] Adam Kaplan, Majid Sarrafzadeh, and Ryan Kastner, "High-Level Data Communication Optimization for Reconfigurable Systems", Workshop on Software Support for Reconfigurable Systems (SSRS), co-located with the IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 2003 [C3] Adam Kaplan, Philip Brisk, and Ryan Kastner, "Data Communication Estimation and Reduction for Reconfigurable Systems", ACM/IEEE Design Automation Conference (DAC), June 2003 [C4] Philip Brisk, Adam Kaplan, and Majid Sarrafzadeh, "Parallel Analysis of the Rijndael Block Cipher", International Conference on Parallel and Distributed Computing and Systems (PDCS), November 2003 [C5] Philip Brisk, Adam Kaplan, and Majid Sarrafzadeh, "Area-Efficient Instruction Set Synthesis For Reconfigurable System-on-Chip Designs", ACM/IEEE Design Automation Conference (DAC), June 2004 [C6] Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, and Majid Sarrafzadeh, "Physically Aware Data Communication Optimization for Hardware Synthesis", International Workshop on Logic and Synthesis (IWLS), June 2005 [C7] Ryan Kastner, Wenrui Gong, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh, Xin Hao, and Forrest Brewer, "Layout Driven Data Communication Optimization for High Level Synthesis", Design, Automation and Test in Europe Conference (DATE), March 2006 [C8] M. Frank Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, and Rocco Tam, "CMP Network-on-Chip Overlaid With Multi-Band RF-Interconnect", accepted for publication at IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 2008 Copyright © 2007 Regents of the University of California All rights reserved.