ENTITY ripple_adder IS PORT (
    av    :  IN  BIT_VECTOR( 3 DOWNTO 0 );
    bv    :  IN  BIT_VECTOR( 3 DOWNTO 0 );
    c_in  :  IN  BIT;
    c_out :  OUT BIT;
    sumv  :  OUT BIT_VECTOR( 3 DOWNTO 0 )
    );
END ripple_adder;

ARCHITECTURE structural OF ripple_adder IS
    SIGNAL c0, c1, c2: BIT;
    COMPONENT full_adder PORT (
        a, b, carry_in  :   IN  BIT;
        sum, carry_out  :   OUT BIT
        );
    END COMPONENT full_adder;
BEGIN
    f0 : full_adder PORT MAP( av(0), bv(0), c_in, sumv(0), c0    );
    f1 : full_adder PORT MAP( av(1), bv(1), c0,   sumv(1), c1    );
    f2 : full_adder PORT MAP( av(2), bv(2), c1,   sumv(2), c2    );
    f3 : full_adder PORT MAP( av(3), bv(3), c2,   sumv(3), c_out );
END structural;