ENTITY full_adder IS PORT (
    a, b, carry_in :    IN  BIT;
    sum, carry_out :    OUT BIT 
    );
END full_adder;

ARCHITECTURE dataflow OF full_adder IS
    SIGNAL x1, x2, x3, x4, y1 : BIT;
BEGIN
    x1 <= a AND b;
    x2 <= a AND carry_in;
    x3 <= b AND carry_in;
    x4 <= x1 OR x2;
    carry_out <= x3 OR x4;
    y1 <= a XOR b;
    sum <= y1 XOR carry_in;
END dataflow;